Deliver quality robust designs with passion for customer satisfaction and project success
Experienced design engineer contributing to the success of multiple high performance ASIC, SPARC
microprocessor, FPGA and hardware systems. Knowledge of complete development cycle from conception
and requirements including micro architecture, documentation, RTL implementation, verification, DFT,
physical design, and timing closure as well as post silicon debug and sustaining. Strong team player,
delivering high quality results with demonstrated success in multiple positions ranging from Member of
Technical Staff (1 - 5) to Management. Work intensely, giving team member technical guidance,
confidence, praise, and completing projects on schedule with winning success.
SystemVerilog, Verilog & RTL Design SVAs and RTL Code Coverage Analysis
Synthesis & Static Timing Analysis Management & Project Leadership
UNIX, VNC, GVIM & Perl Scripting PCB Design & Schematic Capture
Microarchitecture & Specification RTL Linting, Simulation & Waveform
Lab Bring Up, Debug & Validation Xilinx FPGAs & ISE Design Suite; Chipscope
01/1989 to 01/2017
SUN MICROSYSTEMS / ORACLE CORPORATION
Assisted verification team in the validation of debug and transaction visibility functionality writing tests
in the VMM verification framework.
ASIC implementation: maximum clock frequency of 1.2GHz, 28nm, and 61M gates.
Project PCIe Gen3 x8 - Microprocessor Integration: 2010 - 2011
Designed, as part of team, Gen3 x8 PCI Express Root Complex Data Management Unit Core, integrating
onto SPARC T5, M5 and M6 processors.
Administered micro architecture, documentation, RTL implementation, and timing closure (28nm, 500
MHz) of the Interrupt Management Unit.
Project PCIe Gen2 x8 - Microprocessor Integration: 2008 - 2009
Executed Gen2 x8 PCI Express Root Complex Core Data Management Unit integrated onto SPARC T3 and
Created micro architecture, documentation, RTL implementation, and timing closure (40nm, 500 MHz)
of multiple DMU units.
2007: Prototype designed to accelerate Oracle RAC clustering software using PCI Express Gen2 x4 IP
cores as the low level memory interconnect (Xilinx Virtex-II Pro, 250MHz).
01/1989 to Current
Principal Hardware EngineerSUN MICROSYSTEMS / ORACLE CORPORATION － Burlington, MA
Project PCI Express (PCIe) Gen4 x16 Root Complex Common IP: 2015 - Present
Engineering team lead of PCIe Gen4 x16 Root Complex IP Core which manages flow of traffic between
PCIe TLP packets and system memory.
The Data Management Unit (DMU) core Common IP designed to
be integrated in both SPARC processor I/O, and for M-series SPARC processor companion I/O Hub ASIC.
Performed as project lead, scheduling, documenting, prioritizing and overseeing implementation of all
new features, coordinating with cross-discipline engineering teams and upper management.
Collaborated with architecture, design and verification team members, doubling bandwidth throughput
and reorganizing unit modules, improving latency by 30%+ from leveraged design.
Principle designer and owner of several (DMU) units incorporating multiple new I/O features,
improving performance and enhancing system security.
Mentored and coached junior design and verification engineers, accelerating learning curve ramp time,
and ensuring on schedule completion.
EARLIER CAREER HIGHLIGHTS
2004 - 2005: Cluster lead for PCIe Gen1 x8 Host Bridge I/O ASIC.
115nm, 200 MHz, 4.3M gates
2000 - 2002: Engineering Manager - ASIC Derivate Product Group
Managed 7 Direct Reports while Project Lead of Sun Microsystems 1st Second Source ASIC
1998 - 1999: PCI Southbridge I/O ASIC Chip lead integrating Enet, 1394, USB and Ebus interfaces
Served as the Sun Microsystems hardware representative on the 1394 (Firewire) Open Host
Controller Interface (OHCI) Industry Standard Committee.
Education and Training
Bachelor of Science: Electrical EngineeringElectrical Engineering
BSEE: Computer ScienceNortheastern University － Boston, MAComputer Science
ASIC, clustering, hardware, Controller, Data Management, documentation, Engineering Manager, features, Hub, IP, team lead, managing, memory, Microprocessor, 2000, MSI, next, Oracle, PCI, processors, Project Lead, Express, RAM, scheduling, Sun Microsystems 1, Sun Microsystems, SPARC, USB, Validation
Validating Message-Signaled Interrupts by Tracking Interrupt Vectors Assigned to Devices, US Patent No.
8,631,181, Jan 14, 2014