Tools: Synopsys VCS, Synopsys Design compiler, Prime time, Quartus II, ModelSim, Xilinx ISE Web pack, MAGMA, Virtuoso, Cisco Packet Tracer.
Operating System: Unix, Windows
Web application tool: Have experience working in SharePoint & Confluence etc.
Project Management Software: Microsoft Project Layer2/3 switching, Tunneling, QoS, Different topologies and protocol technologies, VoIP services, Broadband services etc.
Tiger IT LtdJanuary 2013 to CurrentSystem Design Engineer
Identify, understand and plan for organizational and human impacts of planned systems, and ensure that new technical requirements are properly integrated with existing processes and skill sets.
Worked on TigerAFIS, a highly scalable fingerprint matching array built on Intel Xeon Processor based server to prevent multiple registration.
To integrate the TigerAFIS in n-tier architecture with the 'matcher controller' service operating on dedicated LINUX and COTS (Commercially off the shelf servers) in high speed RAM.
Coordinate and work closely with SW engineers, QA team and IT departments to support and design the new in house system and propose optimal solutions that focus on process improvement, cost savings, high security, and global competency for clients.
Fastrack Anontex LtdJanuary 2012 to January 2013Design Engineer
RTL Design, Simulation & Functional Verification, Synthesis using Design Compiler of USB2: Physical layer.
Added some features from USB3 to develop the code.
Worked on circuit design & layout for PHY block of USB2 using Virtuoso.
Analyzed timing reports using Prime Time & wrote few Perl scripts for automation of timing report analysis.
Responsible for developing micro architecture module with the help of architecture staff, performed Chip Integration, flow development, Processor based system design and Memory design etc.
Support Physical design and Product Engineering for high volume production.
Baysand Semiconductor Sdn. BhdJanuary 2011 to January 2012Design Engineer
Testing the functionality of various models in Altera Sync RAM.
Worked on Timing analysis using prime time & power analysis using Quartus II.
Worked on circuit design & layout for different memory blocks using Magma.
Tool comparison on G65LA & regression suite for FPGA.
Broadcom Corporation Infrastructure & Networking GroupJanuary 2010 to January 2011San Jose, CA.
In this position, I was responsible for doing test, characterization, and data analysis of high-end network switching devices and OTP testing in a Linux-based lab environment.
Assist with early engineering sample bring-up/debug/test-screen and Prototyping logistics.
Support/track SVK (Signature Verification key) and Reference board/system builds delivered to ENG, SV, S/W, AE, DVT and Customers.
Designed, synthesized, analyzed and optimized an 8 bit microprocessor which implemented a subset of MIPS instruction set using Verilog.
Power Meter Calculation: Designed a Power meter using Verilog which consists of FIFO, register controller, memory, divider, multiplier.
Simulated it by VCS & synthesized it with Design compiler.
27 Bit Adder: Designed a 27bit Carry Look Ahead Adder & simulated it by Cadence Virtuoso.
Simulation of Packet Queuing Behavior in Computer Networks using OMNET++ Simulation Tool.
Published Conference Papers: International Conference Rajib Imran, Monirul Islam, Abdullah-Al-kafi, Synthesizable Digital Phase Locked Loop Implementation in 2013 2nd International Conference on Applied Materials and Electronics Engineering (AMEE 2013) , April 20th , 2013 , Hong Kong.
Published Journal Papers: International Journal 1 Abdullah-Al-Kafi, Rajib Imran, Monirul Islam, Development of FSM based Running Disparity Controlled 8b/10b Encoder/Decoder with Fast Error Detection Mechanism in Hybrid Computing Technology Labs (HCTL) Open International Journal of Technology Innovations and Research (IJTIR) , Volume 2, March 2013, e-ISSN: 2321-1814, ISBN (print) : 978-1-62776-111-6.
2 Monirul Islam, Rajib Imran, Bushra Mahjabeen , On-Chip Techniques for Electromagnetic Interference (EMI) reduction in International Organization of Scientific Research Journal of VLSI and Signal Processing (IOSR-JVSP), Volume 2, Issue 4, May.-Jun.
2013, e-ISSN: 2319-4200, p-ISSN: 2319-4197.
3 Rajib Imran, Monirul Islam Industrial Modified Digital Scrambler & De-scrambler system in Hybrid Computing Technology Labs (HCTL) Open Science and Technology Letters (STL), Edition on Reconfigurable Computing - Embedded, FPGA based, VLSI and ASIC Designs, June 2013, ISBN (Print): 978-1-62776-963-1.
MSEE , San Jose State University Military Institute of Science & TechnologyBSEECA, USA