Acquire a hardware engineer position in a dynamic team to propel company's growth using my semiconductor knowledge
and hands-on experience with EDA tools.
Operating Systems Programming Languages Test Tools Backend Tools/ Software's
Design Verilog language.
Xilinx ISE compiler AREAS OF INTEREST High speed and low power digital design.
Design for test and test development.
Automatic Place and route.
Product Development Intern06/2013 to 08/2013IntelHillsboro, OR
Developed software for product development and test infrastructure working mainly with Haswell and Broadwell.
Developed Engineering Data Collection capabilities (using Perl) that interface with the Design Validation environment used by the testers to enable the automated collection of data such as Vmin and Fmax.
Acquired knowledge on flow of Silicon bring-up using test bench, active debug and validation of IO, power and other tests on the tester/Burn-in equipment.
Collaborated on cross-functional teams consisting of product engineers, technical leads and Fab technicians to create user stories, plan iterations, and track tasks using Rally.
Graduate Assistant10/2013 to 05/2014University of IllinoisChicago, IL
College of Dentistry) in providing top-quality IT services and solutions to students, faculty and doctors in the dental school; revamped the IT infrastructure to ensure the accreditation of dental school.
Responsible for Software/Hardware troubleshooting and network administration; Successful in taking ownership of various dynamic issues and providing real-time solutions.
08/2012 to 12/2012
Designed and implemented a 1K-bit SRAM (180 nm) in a minimal area of 26427µm.
Observed read delay, write 2 delay and pre-charge time of SRAM was 934.4ps, 854ps and 147ps respectively.
Full Custom Layout of the 1Kbit SRAM using Virtuoso Layout editor.
DRC and LVS verified using ASSURA and the parasitic extraction and post layout simulation performed using SPECTRE.
Test volume and time reduction Jan 2013 May 2013.
Achieved ATPG test vector compression of 70% by designing Compression algorithms (Huffman encoding) using C which lead to reduction in memory requirement and fast application time.
Performed fault simulation on ISCA89 benchmark circuits and the results revealed RTPG (Perl script) attained similar fault coverage (98%) compared to ATPG (Atalanta-M 2.0) for elementary circuits.
The results of complex circuits illustrated ATPG (97%) was superior to RTPG (82%).
4-bit ALU design (Verilog) Aug 2012 Dec 2012.
Designed and tested a 4-bit synchronous ALU which performed 4-bit addition, subtraction, 1's & 2's complement, 4-bit binary to gray code conversion, 4-bit NAND and 4 bit NOR operation.
Enhanced the speed of arithmetic operations using carry look ahead adders & the logic unit was constructed using fundamental gates.
Five-stage pipelined MIPS processor Aug 2012 Dec 2012.
Implemented a 32-bit pipelined processor using Verilog on a Xilinx Virtex-3 which comprised of ALU, control logic, data path unit, register file and memory for data and instruction.
Designed combinational circuits for ALU computations and sequential circuits to represent state elements.
Processor supported 32-bit R-type, I-type and J-type instructions.
Hardware implementation of canny edge detection algorithm (VHDL) Jan 2011 May 2012.
Developed, simulated and synthesized the entire system using ALTERA DE II kit.
Smoothed the input image by Gaussian mask.
Coefficient (coe) file of the input image was generated using MATLAB.
This coe file stored in Block ROM was processed using the canny edge detection algorithm.
Used VGA interfacing to display the output image on the monitor.
Audio amplifier design (HSPICE) Jan 2013 May 2013.
Devised a two-channel Stereo audio amplifier with minimum gain 3 DB and maximum gain 20 DB and implemented as an analog integrated circuit using summing amplifiers, voltage amplifiers and power amplifiers.
Tackled the challenge of producing a stable DC power supply of 12V from a 120 Vrms household power supply by inserting capacitors and voltage regulators at various stages of the circuits.
Message passing interface on ARGO cluster (C language) Aug 2013 Dec 2013.
Developed MPI programs using C and MPI standard libraries on ARGO cluster to efficiently distribute the large input data among the processing nodes arranged in ring or hypercube topology.
Decreased the execution time by 60% on application like Matrix multiplication by effective load balancing.
Master of Science: Electrical Engineering Digital logic and RTL designMay 2014University Of Illinois At ChicagoGPA: GPA: 3.25/4.00Electrical Engineering Digital logic and RTL design GPA: 3.25/4.00 Digital system design, Analog and mixed VLSI, Introduction to VLSI, Advanced VLSI, Advanced computer architecture, Testing and reliability of digital circuits, Computer algorithms and Semiconductor device physics.
Bachelor of Science: Electrical EngineeringMay 2012SASTRA UniversityIndiaElectrical Engineering Microprocessors (8086), Microcontrollers (8051) and linear integrated circuits. CGPA: 7.6/10.0