Tools: Visual Studio 2012, Gerrit, Perforce
1. MMI App (WP7)
UI based app for a one touch solution to test functionalities of FM, Vibration, Camera, Battery
cycle, Proximity Sensors, Bluetooth, Airplane Mode, Wi-Fi and so on. Customized the
app for TCL (client) and included both Chinese and English language support in UI.
2. Vellamo for WindowsPhone8
Mobile Benchmark App that analyzes the browser performance and CPU functionalities like
Floating point operations, Zoom-In Zoom-out view, Page Load Performance, Color Fading
performance, 3D view and many more on a WP8 and gives a composite score. It has a
rich collection of 8 HTML benchmarks (Browser) and 2 Metal benchmarks (CPU).
Engineer II07/2012 to 06/2014Qualcomm India Pvt Ltd, Bangalore Windows Software Team, Bangalore Development CenterHyderabad, India
Mobile Applications(Native and HTML) development Test Automation Tool development Verification Tool development Experience in Linux and Windows Environment Worked on developing CASE (Continuous Assessment Software Execution) system which is used to monitor and test Windows Phone OS releases by Microsoft for various Qualcomm Chipsets/Product Lines like 8974, 8227, 8930, dual sim 8x26 and low end 8x12.
Also Automated many manually performed time consuming tests like Boot & Shutdown time measuring, driver exercising, Video-Audio Playback, Crash Dump Collection tests.
Worked on developing benchmark WP8 Apps to test Browser and CPU performances for various chipsets.
Closely worked with the San Diego team and Microsoft.
01/2009 to 06/2012Whizchip India Pvt Ltd AXIOM Ltd
Joined as a Post Graduate Intern and later got absorbed as full time resource.
Actively involed in developing Xplan, a Whizchip proprietary methodology tool for functional verification closure used in the Semiconductor Industry.
Auto Sequence Generation feature of Xplan addresses the challenge of True Random Sequence Coverage to be achieved with less time, least memory utilization and with minimal human intervention.
Xplan2Verilog and Xplan2SV features auto dump testbenches in Verilog, System Verilog, and Vera constraints and coverage codes for different methodologies like OVM, VMM and RVM.
Thereby saving a lot of development time and resources.
These codes directly work on the XPlan file which represents the functional coverage model of the design.
The coverage model is given as input through a simple XPlan GUI, the constraints and coverage codes can be auto-generated through a click of a button.
Register Set Device Driver, a software tool that acts as one stop solution for processor design verification used by verification engineers.
Register library contains relevant bits' info of each register used by block under test.
User simply has to login using reg GUI and modify necessary register bit's value in the editable section.
A verilog/system verilog code is dumped containing APIs used to modify the actual registers.
A very simple-to-use yet effective way of handling verification issues.
Language: Perl, C++ Platform: Linux Key Roles and Responsibilities: Developed the Master module Participated in integration of the tool to the XPlan GUI.
Complete packaging for customer quality release right from alpha release to final product release.
Actively participated in customer demos and provided client support.
Qualstar June 2014 - Automation of KPI testcases Qualstar 2013 for introducing and developing the very first Mobile Benchmark App on Windows Phone.
Performance recognition (2010) reward for timely action and quality of execution in the XPlan Project.
Topper in the batch (Masters degree) Represented and Won Inter-Collegiate Fashion Show.
Masters degree: Embedded System Design2009Manipal UniversityIndiaEmbedded System Design
Bachelor of Engineering: Electronics & Communication2007Vishweshwaraiah Technological UniversityIndiaElectronics & Communication