Implementation of a basic 5 stage MIPS Pipeline system and analysis of advantages of Forwarding and Branch Prediction.
Behavior of a 5 state pipeline system with and without forwarding and branch prediction was simulated using C and the results were analyzed in terms of the number of data hazards encountered, execution time and the speed up achieved.
A detailed analysis of various memory level organizations and the cache structure by using IEEE reference papers and study of a proposed method called the Selective Victim Caching which aims at improving miss rates while accessing the memory there by speeding up the overall execution of the instructions.
Several benchmarks were compared with victim caching technique and a report was published.
DIGITAL IC DESIGN
High speed pipelined FPGA implementation of AES Encryption and Decryption.
Developed a synthesizable Verilog model at RTL level followed by validation of the RTL model using ModelSim, synthesized in Xilinx ISE and implemented in Xilinx Spartan 3E FPGA.
Design and characterization of a 12 cell standard cell library containing most essential combinational and sequential logic, where implementation of a schematic using the Composer Schematic and physical design layout using Virtuoso Layout Editor were performed and designs were verified for design rules with DRC and verified structurally against schematic with the LVS software.
Design of a 64 input NOR gate for high performance and low power applications with various logic families and their significance were analyzed considering various factors the affect the performance of each design and the best design is chosen for the application.
All circuits and simulations were done using Cadence composer.
Design and Validation of a Two Out of Five Code Error Detector.
A sequential model, a dataflow model and a structural model of the Error Detector were designed in VHDL and the functionality of each of these models was verified using a test bench also coded in VHDL.
Design and Validation of 8 deep dual port FIFO.
RTL description of the FIFO with independent read and writes ports were written in VHDL and the same was validated using a VHDL test bench.
ANALOG IC DESIGN
Getting acquainted with design environment, particularly the schematic entry and simulation tools, and use those tools to analyze the behavior of Inverter.
Three different inverter configurations were analyzed.
The Resistive load, the Diode Load and the classic CMOS were drawn using Cadence composer and DC and Transient Responses were observed for these three topologies.
Design and implementation of a Phase Locked Loop System to generate a stable clock frequency and analyze its use in the digital environment.
POST SILICON ELECTRICAL VALIDATION:.
Analysis of Crosstalk in Signal Integrity, studied the effects of Crosstalk on Signal Integrity.
Measured crosstalk using Electrical Validation Board.
Solutions to reduce the effects of crosstalk were also suggested and a research paper was published.
Customer Support Executive June 2011 to July 2012Sree Sathya Interiors Pvt Ltd
Provided quick debug or troubleshooting of issues.
Effective communication of the issues at hand and providing a quick and robust solution.
Education and Training
Bachelor of Engineering : Electrical and Electronics Engineering, May 2011ANNA UNIVERSITY － Chennai, INDIAElectrical and Electronics Engineering MASTER OF SCIENCE
Computer Architecture, IC Technologies, Advanced Computer Architecture, Digital IC Design, ASIC Modelling, Synthesis and Post Silicon Electrical Validation.
BACHELOR OF ENGINEERING
Microprocessors and Microcontrollers, Electronic Devices, Digital Logic Circuits, Linear Integrated Circuits and Control Systems.
Master of Science : Electrical and Computer Engineering, Dec 2014PORTLAND STATE UNIVERSITY － Portland, ORGPA: GPA: 3.4 / 4.0Electrical and Computer Engineering GPA: 3.4 / 4.0 Focused primarily on Digital IC Design including RTL coding, logic verification, synthesis, static timing analysis, performance verification and electrical validation.