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Senior Design Engineer / Manager (Grade L9) Resume Example

Resume Score: 80%

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SENIOR DESIGN ENGINEER / MANAGER (GRADE L9)
Professional Summary
A dependable and dedicated Professional carrying a rich blend of Engineering and Management experience for 14 years, with an enthusiasm and willingness to take on added responsibilities by focussing on planned objectives and tight deadlines. A tech-savvy Manager with keen interest and knowledge in all aspects of Project Management with parallel excellence in technology and Process reengineering.
Skills

ASIC Development

Product Development

Customer Satisfaction and Service Oriented

Highly Organized

Requirements Definition and Analysis

Leadership, Team Building and Mentoring

Efficient Cross-Functional Communicator

Project Management

Quality Assurance

Conflict resolution

Awards
  • Broadcom Employee Spot Award (2010, 2011, 2012, 2013, 2015)
  • Outstanding Performance in Customer Support (2006)
  • Best Performer Award (2005)
  • Gold Medalist in Post-Graduation (2003)
Work History
Senior Design Engineer / Manager (Grade L9), 03/2016 to Current
Intel Corporation – Santa Clara, CA

Working as a Architect / Digital Design Engineer for the 5G SOC Architecture, a newly formed team for the establishment of Industry's first Cellular 5G

  • Lead member in all the stages of the Project from Requirements gathering to Roll out of each planned Release
  • Strong communications within and across the varied cross functional teams to accomplish smooth operations flow and attain successful results
  • Track and control the Project phases to match accomplishments against the set up goals/actual plan
  • Coach and mentor new team members and others on need basis for better performance outcomes

Technical Highlights

  • Third Party IP's Evaluation (ARM Processor, PCIe, DDR, SerdesPhy, SSI, I2C, NoC)
  • PCIe CPU Subsystem Architecture, PCIe Integration
  • Process Node selection (14nm/10nm) 
  • Performance - Latency Calculation
  • Power Analysis, Low Power Architecture
  • Power Switches Estimation
  • Design and Debug Architecture

Senior Principal Engineer IC Design, 01/2007 to 02/2016
Broadcom Corporation – Sunnyvale, CA

5G WiFi - Industry's First 802.11ac chip: BCM4360

  • Worked as a Chip Lead with responsibilities from requirements gathering, Product definition to Production / Project Close out with timely Stakeholder Communications
  • Collaborated with various cross functional teams (Systems, Radio, SOC Architecture, Marketing, Package, Operations to name a few) to ensure process flow via appropriate communication channels
  • Trained, mentored and guided a team of smart Engineers for successful outcomes
  • Implemented innovative techniques that exceeded Company Objectives (a new Pin Muxing Technique for Low pincount usage still supporting multiple Board options)
  • End Customers: Apple-Mac Air, Apple-Router, Buffalo, NetGear, Cisco

802.11 MAC Architecture

  • Worked as a Tranmsit path Design Lead for 802.11 MAC Blocks
  • Successfully Lead the Project from initiation to Close out
  • Actively tracked the Project Status and accomplishments for proper monitoring and control
  • Coordinated between all the teams involved to ensure smooth process flow

Other Projects

  • Chip Lead for BCM4360RFTC - a Test chip where more key blocks got integrated and tested with integrated AFE/Radio
  • Design Lead for WiFi SOC - Low Power Architecture
  • Integration Lead for SoC Integration for chips BCM43236(USB), BCM43224(PCIE)
  • Design Verification Lead for 802.11n 2x2 MIMO Phy with Integrated Radio




Senior Design Engineer, 12/2002 to 12/2006
Vinchip Systems – Sanjose, CA
  • Game Console SOC (Nintendo Wii) - Lead Consultant  and successfully Implemented the SOC Interconnect Architecture, Implementation of AHB subsystem
  • Worked as a Design Lead for USB2.0 Embedded Host Controller by guiding a team of 3 Engineers. Customers included PictoLogic, Myson Inc, Focus Enhancements, Denali Software.
  • Worked as a Design Lead for I2S Interface for USB2.0 Audio Device Controller
  • Board Design Lead for customer demo PCB board with Altera's Stratix and Cyclone FPGA, which is the primary vehicle for company's demo with this USB controllers. 

  ​




Achievements and Accolades
  • ATE Bringup Turnaround time [12 weeks to 2 weeks] by implementing a new Process where the Lab bring up can be directly used for ATE patterns. Got Recognized by the whole Broadcom business groups and adapt to this process. 
  • Enhancing  the Verification bench for Emulation purposes , which helps in debugging the realtime lab issues to simualtion in lightning speed.
Education
Master of Science: VLSI-CAD, 2001 - 2003
Manipal Academy of Higher Education - Karnataka, India
Gold Medalist in Post Graduation
B.E/B.Tech: Electrical and Electronics Engineering, 1997 - 2001
Madurai Kamaraj University - India
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Resumes, and other information uploaded or provided by the user, are considered User Content governed by our Terms & Conditions. As such, it is not owned by us, and it is the user who retains ownership over such content.

Resume Overview

Companies Worked For:

  • Intel Corporation
  • Broadcom Corporation
  • Vinchip Systems

School Attended

  • Manipal Academy of Higher Education
  • Madurai Kamaraj University

Job Titles Held:

  • Senior Design Engineer / Manager (Grade L9)
  • Senior Principal Engineer IC Design
  • Senior Design Engineer

Degrees

  • Master of Science : VLSI-CAD , 2001 - 2003
    B.E/B.Tech : Electrical and Electronics Engineering , 1997 - 2001

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