Self-motivated Electrical Engineer with 3+ years experience and strong background in semiconductor device physics and semiconductor process seeking entry/junior level position as a Design/Device Engineer. Core strengths include microelectronics, nanoelectronics and CMOS Design and Analysis of Analog/Digital Integrated Circuits, device fabrication and device characterization in a clean room environment. and detail oriented with excellent writing, listening, and interpersonal communication skills.
- Technical writing
- Python
- C++
- Orcad Capture
- Verilog/VHDL
- Sentaurus TCAD
- Cadence
- PSpice
- Microwind
- JMP
- Modelsim
- Microsoft Office
- Lithography Process
- Scanning Electron Microscopy (SEM)
- ALD Process
- Device Evaluation and Characterization
- Atomistik Toolkit
- Analog/Digital IC Design
- Multisim
- Labview
- Windows/Linux/Unix
- Design of Experiments
- Perl
- Root cause analysis
- Thesis: Two-Dimensional Materials: Doping-Induced Variation, Heterojunction FETs and Hybrid Multilayers
- Coursework in VLSI Test Concepts, VLSI Design and Layout, CMOS Analog and Digital Integrated Circuits, Modern Systems Theory, MOS Devices, Nanoelectronics, Device Characterization
- https://www.linkedin.com/in/Jessica-Claire-2b41b299
Cambridge, MA, 01/2017 - 08/2018
- Designed research experiments to improve the process of device fabrication for Novel two dimensional semiconductors.
- Improved methods and procedures for processes, measurements, documenting and work flow techniques
- Produced detailed oral and written reports of device simulations and analyzed result output
- Discovered and explained the source of device-to-device variation and related key processing parameters
- Conducted reliability testing including Stress Tests on devices and developed optimized algorithm to analyze test data.
- Performed detailed component analysis using oscilloscope, X-Ray, curve-tracer, and analyzed CSAM and SEM images
Issaquah, WA, 08/2013 - 12/2016
- Performed electrical characterization of device test structures and improved model for extracting device parameters
- Developed device modeling techniques which aided theoretical support for novel two-dimensional device designs
- Investigated source of device-to-device variation, related key device parameters and provided explanations to understand device behavior and avert failure
- Designed, simulated nanoscale two-dimensional Field Effect Transistors (FETs) and characterization
- Provided process support (including flow design, unit process development and optimization) to colleagues with research needs.
- Worked on two dimensional semiconductors, studying effects and behavior of novel materials in field effect devices.
Terre Haute, IN, 08/2013 - 12/2014
- Checked assignments, proctored tests, and provided grades according to university standards.
- Taught weekly recitation sessions to Junior and Senior level students in Linear Circuits and CMOS Analog/Digital Integrated Circuit Design
- Conducted research in novel semiconductor materials with team of ten graduates and faculty.
- Mentored students through office hours and one-on-one communication.
- Performed LVS and DRC verification of layouts in IC design
- Developed analog integrated circuits from specification to layout using Cadence/Microwind in Analog/Digital design coursework
- Implemented VHDL code in digital design, performed simulations and timing checks to ensure proper functionality in Digital circuits.
- Student Member, Institute of Electrical and Electronics Engineers (IEEE)
- National Society of Black Engineers (NSBE)
- American Chemical Society (ACS)
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School Attended
- George Mason University
- Kwame Nkrumah University of Science And Technology
Job Titles Held:
- Research Associate
- Graduate Research Assistant
- Graduate Teaching Assistant
Degrees
- Master of Science
- Bachelor of Science
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