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Electrical Engineer II Resume Example

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ELECTRICAL ENGINEER II
Professional Summary

To employ my accrued knowledge and skills to support and contribute to a team which produces high quality outputs in the hardware design and development process.

Skills
  • C, C++, java, VHDL, Verilog, DOS, Python
  • Environments: MATLAB, ORCAD Capture CIS, Quartus II, Altium Designer (summer 2012 up to Altium 18),
  • HDL Designer, FlashPRO, Vivado, ISE, LTSpice, LTPOWERCAD
  • Operating Systems: Windows, Unix, Linux (Ubuntu)
  • Hardware: Tektronix TDS 3012B Oscilloscope, Fluke 287, Fluke 726, Function Generator, Programmable
  • Development Boards, Soldering Station, HP Agilent 1661c Logic Analyzer, AstroMED DASH 18x, USBee Rx
  • Logic analyzer, Saleae Logic analyzers, Xilinx FPGAs (Spartan 2A, Spartan 6, 7 series (including Zynq PS and
  • PL)), Avnet MicroZed (7010 and 7020), AC701 development board, Zest ET1/ETM1 gigabit offload engine
  • Automation, Validation
  • C, Verilog
  • C++, VHDL
  • Cable
  • Calibration
  • Hardware
  • Documentation
  • DOS
  • Electronics
  • Function Generator
  • HP
  • Java
  • Layout
  • Linux
  • Logic
  • Logic Analyzer
  • MATLAB
  • Windows
  • Operating Systems
  • ORCAD
  • Oscilloscope
  • Peak
  • PL
  • Processes
  • Python
  • Quality
  • Scripts
  • Script
  • Soldering
  • TDS
  • Troubleshooting
  • Unix
Work History
Electrical Engineer II, 10/2016 to Current
Company Name – City, State
  • Created the PCB layout and schematic capture for front end electronics for CdZnTe semiconductor detectors including complex stack-ups such as HDI with Ormet interconnects, as well as rigid-flex, and flex constructions.
  • Designed ceramic substrates and PCBs optimized for small amplitude charge signals (on the order of femto- Coulombs per pulse) from CdZnTe detectors to several different ASICs.
  • Created the PCB layout and schematic capture for test and bring up boards for several projects.
  • Created test set up and performed external pulser testing on CdZnTe pixelated detectors utilizing self-made capacitive coupling to anode pads to inject charge representative of isotopic radiative sources.
  • Created calibration procedures utilizing X-Ray tubes instead of isotopic radiative sources.
  • Implemented complex flat field correction algorithm in VHDL on a Xilinx 7 series target.
  • Fixed issues in several designs which were susceptible to EMI.
  • Created several Python scripts for stability testing, pulser analysis, Gerber filename standardization, and peak spread measurements.
  • Modified HDL for several projects in order to fix customer issues and bugs including pixel mapping issues as well as LVDS and SPI communication issues.
  • Created HDL for pixel summation on keV-351DW project utilizing VHDL.
  • Lead hardware and HDL design for level gauge application of CdZnTe detectors.
  • Updated old HDL designs in VHDL and Verilog to uniform language and to a clean, organized architecture, creating documentation so further addition and update could be performed more efficiently.
  • Lead electrical troubleshooting efforts for several projects.
  • Provided full electrical support for several projects including cable design and build, board bring up and testing, vendor interaction and handling RMA issues.
  • Successfully lead redesign efforts for several projects fixing design issues found in prototype stage.
  • Designed HV filtering and Cathode signal coupling PCBs for use with photonic detectors.
  • Performed Hi-Pot testing for HV portions of several projects.
Electrical Engineer I, 01/2016 to 10/2016
Company Name – City, State
  • Created the PCB layout and schematic capture for front end electronics for CdZnTe semiconductor detectors.
  • Designed ceramic substrates and PCBs optimized for small amplitude current signals (on the order of femto- Coulombs per pulse) from the CdZnTe detectors to several different ASICs.
  • Created and performed V&V test plans providing results to satisfy customer requirements.
  • Successfully lead the electronics design for the keV-360 project.
  • Lead efforts in improving the fabrication and documentation processes.
Hardware Engineer, 02/2014 to Current
Company Name – City, State
  • Created the PCB layout and schematic capture for several interface boards and backplanes used in testing the ALS platform for compliance with NRC RG 1.105.
  • Provided engineering support and troubleshooting during the EMC testing of the Diablo Canyon PPS configuration of the ALS platform.
  • This included testing to EN 61000-6-2, EN 61000-6-4, MIL-STD-461E, IEC 61000-4-2, IEC 61000-4-3, IEC 61000-4-4, IEC 61000-4-5, IEC 61000-4-6, IEC 61000-4-12, IEC 61000-4-16.
  • Successfully lead the validation of the monitoring software used in the EMC tests of the ALS platform.
  • Prepared hardware drawings for a nuclear I&C test bed which utilized the AC160 platform.
  • Took responsibility of hardware of the automated test platform used for manufacturing testing and design validation of the ALS platform.
  • Analyzed the current procedures and processes used to verify the setup and to maintain the system and identified gaps which allowed errors to go uncaught.
  • Increased the rigor of the setup verification to remove the procedural gaps that allowed errors to remain unfound.
  • Changed manufacturing test procedures for the ALS platform to reduce human error and increase automation and quality.
  • Created a script which allowed barcodes to be used to automatically pull the correct images to be programmed on to the ALS boards.
Systems Engineer, 11/2013 to 02/2014
Company Name – City, State
  • Provided engineering support and troubleshooting during the fault and isolation barrier testing effort for the ALS platform.
  • This included testing to IEEE Std 384-1992 as endorsed by NRC Regulatory Guide 1.75.
  • Brought up several interface boards for the manufacturing testing of the ALS II platform through the hardware development process from customer requirements to finished product.
  • Designs were made in Altium Designer and boards manufactured by subcontractor of Westinghouse Electric Company, LLC.
Education
Master of Science: Electrical EngineeringUniversity of Pittsburgh - City, State
GPA: 3.85
BSE: Computer EngineeringCum Laude, GPA: 3.474
Bachelor of Science: EngineeringUniversity of Pittsburgh - City, State
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Resume Overview

School Attended

  • University of Pittsburgh

Job Titles Held:

  • Electrical Engineer II
  • Electrical Engineer I
  • Hardware Engineer
  • Systems Engineer

Degrees

  • Master of Science : Electrical Engineering
    BSE : Computer Engineering
    Bachelor of Science : Engineering

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