Design Verification Engineer with four years of experience in verifying custom Ethernet IP and complex systems using System Verilog (UVM), Verilog, Perl and Shell Scripting. Experienced in full verification flow. Experience in design, Spyglass RTL analysis and Synthesis. Thorough understanding Ethernet IEEE 802.3 standard.
Advanced diploma in RTOS and Embedded Systems 6/2009 - 12/2009
Assembly and Embedded C Programming on AVR Atmega128 and ARM 7 LPC2148.
Communication protocols: RS-232, I2C, and SPI), Data Structures, RTOS Porting.
Application Development using uC-OS II.
Embedded Linux Programming and Application Development such as ‘chat' applications, primary and backup server using socket programming.
Courses: ASIC Design, ASIC Verification, Computer Architecture, Architecture of Parallel Computer, Advanced Microprocessors
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