Results-focused FPGA & ASIC professional offering 17 years of IC Design and Project Management leadership experience. Successful in building dynamic teams in various geographies with exceptional results.
Status: Permanent Resident of the United States.
FPGA & IP DESIGN
Design skills: Analog/Mixed signal design, Digital design, ASIC Backend design, Place & Route (P&R), Static Timing
Analysis (STA), Logic Equivalent Check (LEC), DFT and Test insertion flow.
Process knowledge: Industry's most advanced Intel 14nm FinFET process.
Tools: HSPICE, HSIM, Star-RC XT, Virtuoso, Verilog-A/D, OVM, UVM, Design Compiler, CDC, IC Compiler, PrimeTime, PT-SI, Nanotime, Formality, ESP-CV and Tetramax. Programming: C++, TCL, Perl & Unix.
Programming: C++, TCL, Perl & Unix.
Key Project/Program Management and Technical Achievements
U.S. Patents (10)
ASIC Physical Design
Corporate Program Management
Core Fabric and IO PHY Design
Global Design Verification
Digitally Assisted Analog (DAA) development
High Speed Analog IP Design
HardCopy Structured ASIC Design
Design-For-Test (DFT) for Hardcopy II Structured ASIC
Stratix II FPGA Full-Chip Logic Verification
Stratix II FPGA Embedded Memory Design
Cyclone I Low-Cost FPGA Design
APEX-II FPGA General Purpose and LVDS PLL Design
VLSI Mask Design and Development
Design and Integration of Telecommunication Systems.
Core member of the CTO office in Altera.
Proficient in spoken and written English, Mandarin, Cantonese and Malay.
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