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Jessica Claire
  • Montgomery Street, San Francisco, CA 94105
  • Home: (555) 432-1000
  • Cell:
Executive Summary

Results-focused FPGA & ASIC professional offering 17 years of IC Design and Project Management leadership experience. Successful in building dynamic teams in various geographies with exceptional results.

Status: Permanent Resident of the United States.

Core Qualifications


  • Core IPs, Routing Fabric and Configuration system definition and design for Altera's High-End, Mid-Range and Low-Cost FPGAs.
  • FPGA Design and Architectures from 250nm to Altera's latest Stratix-10 FPGA with HyperFlex architecture in 14nm FinFET.
  • High speed SERDES design up to 28Gbps.
  • Low power/Low jitter PLL design.
  • Digitally Assisted Analog (Micro-controller to calibrate PMA and DDR systems).
  • Embedded Memory design.
  • DFT design and test insertion flow development.
  • IP and Full-chip Design Verification.


  • Physical design for IPs and SoC/Embedded Processors (ARM Cortex A9 & A53).
  • Taped out multiple SoCs involving synthesis, formal verification, timing constraint development, floor-plan, IO planning, P&R, CTS, Timing, SI, Low power and physical signoff.
  • Define scenarios (corners and modes) strategy for complete timing convergence.
  • Drive constraints management and implementation.
  • Timing convergence, verification, ECO implementation and closure criteria.
  • Proven management skill in building teams for high performance outputs.
  • Managed Global teams with more than 50 headcount with Senior Managers and Principal Engineers as direct reports.
  • Excellent people development skills. Developed employees to Senior Managers and Principal Engineers.
  • Interacted with Category One customers from design concept to silicon production.

Design skills: Analog/Mixed signal design, Digital design, ASIC Backend design, Place & Route (P&R), Static Timing

Analysis (STA), Logic Equivalent Check (LEC), DFT and Test insertion flow.

Process knowledge: Industry's most advanced Intel 14nm FinFET process.

Tools: HSPICE, HSIM, Star-RC XT, Virtuoso, Verilog-A/D, OVM, UVM, Design Compiler, CDC, IC Compiler, PrimeTime, PT-SI, Nanotime, Formality, ESP-CV and Tetramax.

Programming: C++, TCL, Perl & Unix.


Key Project/Program Management and Technical Achievements

  • Designed the Core Fabric in Stratix-10 FPGA for HyperFlex to double the Core performance from Arria-10.
  • Led the Global Design Verification team to tapeout Arria-10 with functional silicon.
  • Achieved first silicon success for SoCs in Arria-10 SoC FPGAs.
  • Designed the Micro-controller calibration system for SERDES. Fully functional in the first Arria-10 silicon.
  • Achieved first silicon success for SERDES and PLL in 28nm Cyclone-V and Arria-V FPGAs.
  • Architected and designed a 3.125Gbps Interpolator-based Clock-Data-Recovery (iCDR) system in 60nm Cyclone IV GX. Fully functional in the first silicon.
  • Built Altera Penang HardCopy Design Center and taped out more than 80% of the worldwide FPGA-to-ASIC conversions within 2 years.
  • Developed the test insertion flow in HardCopy Structured ASIC. Fully functional in the first silicon.

U.S. Patents (10)

  • Programmable logic with pipelined memory operation.
  • Voltage-based timing control of memory bit lines Real time feedback compensation of programmable logic memory (3x).
  • Clock signal networks for Structured ASIC devices (2x).
  • Techniques for precision biasing output driver for a calibrated on-chip termination circuit.
  • Heterogeneous physical media attachment circuitry for integrated circuit devices.
  • Techniques for varying frequencies of periodic signals.
  • Techniques for varying phase shifts in periodic signals Invention disclosure.
  • A deadzone-free digital clock-data recovery (CDR) system (USPTO review in progress).
Professional Experience
SENIOR MANAGER, 1999 to Current
Mayer Hoffman Mccann P.C.Cumberland, MD,

ASIC Physical Design

  • Leading the ASIC Physical design team to deliver physical designs for the IPs and SoC / Embedded processors for Arria-10 (A9 Dual-Core, 20nm) and Stratix-10 (A53 Quad-Core, 14nm).
  • Deployed best physical design recipe to enable low power and high performance SoC.
  • Defined the SoC/Embedded Processor deployment strategy across Stratix-10 family members.

Corporate Program Management

  • Chaired the Stratix-10 Core Team meeting & work with representatives from IC Engineering, Software, Product Planning/Marketing, Business Units and Product/Test Engineering to steer the program to the right direction.
  • Provided updates to the Executive staffs on program status, schedule, development cost, risks, issues and mitigation plans.
  • Established KPI (Development cost, product cost, schedule, performance, power & etc.) to monitor and project the Stratix-10 program health.
  • Created the Change Control process to evaluate new requests and make decisions in consideration of business opportunity, development/product cost and schedule.

Core Fabric and IO PHY Design

  • Led a Design and Layout team to define, design and implement the Core Fabric and IO PHY for Altera's High-end, Mid-range and Low-cost FPGAs.
  • Innovated FPGA Core Fabric and interface architecture to save die size significantly while hitting the Hyperflex goal of 2X of Arria-10 Core performance.
  • Organized Altera's Worldwide FPGA Core Fabric Summit to enable design implementation and verification plan for the Core Fabric and configuration system.
  • Re-designed the Stratix-10 Configurable RAM (CRAM) for optimum balance between die size and power.
  • Re-designed the Stratix-10 Embedded Memory to save power significantly from Arria-10.

Global Design Verification

  • Led the Global Full-chip & IP design verification team in the 20nm Arria-10 FPGA. First silicon functional.
  • Developed Mixed Signals/Analog verification flow to ensure RTL models and schematic are equivalent.
  • Unified metrics for comprehensive test coverage and bug trend tracking.

Digitally Assisted Analog (DAA) development

  • Led a team of design engineers to develop DAA using Nios II to calibrate SERDES/Transceiver for optimum performance.
  • Achieved first silicon success with the Nios II calibration system working as expected.

High Speed Analog IP Design

  • Led the Penang Analog team to design Transceivers / PMA (Physical Media Attachment) and PLLs in 40nm, 28nm and 20nm process nodes.
  • Established a highly competitive team in Penang capable of running multiple projects in parallel with aggressive schedule.
  • Co-designed the PMA & PLL with San Jose team on the 20nm Arria-10 GT/GX (28G), 28nm Stratix-V GX (14G) & Arria-V GX/GT (10G) and 40nm Stratix-IV GX/GT (11.3G).
  • Fully owned the PMA & PLL in the 60nm Cyclone IV GX (3.125G), 28nm Cyclone-V GX/GT (5Gbps), 40nm Arria-II GX (3.75G) & HardCopy III/IV Structured ASIC devices.
  • Architected and designed a 3.125G Interpolator-based Clock-Data-Recovery (iCDR) system with Spread-Spectrum Clocking (SSC) in the 60nm Cyclone IV GX.

HardCopy Structured ASIC Design

  • Setup Altera Penang Hardcopy Design Center (HCDC) to convert customer designs from FPGA to Stratix Hardcopy and Hardcopy II Structured ASIC devices.
  • Increased headcount of the Penang HCDC group by 400% and handled more than 80% of the total design conversions worldwide within 2 years.
  • Taped out customer designs with an average 5-week design conversion turn-around-time (Alcatel-Lucent, EMC, Ericsson, Fujitsu, Honeywell, Huawei, Motorola, NEC, Nokia-Siemens Network, Olympus, Rockwell Collins, Samsung, Sony & many more).
  • Guided the Customers and Field Application Engineers on FPGA prototyping. Conducted design reviews with customers from all over the world.

Design-For-Test (DFT) for Hardcopy II Structured ASIC

  • Defined and implemented test features at block & full-chip level for the Hardcopy II devices.
  • Developed the test insertion flow, logic verification and timing closure methodology.
  • All test features were fully functional in every Hardcopy II device family members.

Stratix II FPGA Full-Chip Logic Verification

  • Led a team to perform full-chip logic verification for the entire Stratix II product family.
  • No functional error found in the silicon in the Stratix II devices.

Stratix II FPGA Embedded Memory Design

  • Managed a team to design the Medium & Small Embedded Array Memory Blocks in Stratix II.
  • Improved Fmax by 40% with block size reduction of 40% from the Stratix-I memory.
  • The memory blocks performed as expected in the first silicon of all the Stratix II devices.

Cyclone I Low-Cost FPGA Design

  • Collaborated with San Jose IC Design to design the Cyclone 1C6 and 1C3 devices.
  • Automated the schematic generation and integration for the entire Cyclone product family.
  • Taped out both devices ahead of schedule and achieved first silicon success.

APEX-II FPGA General Purpose and LVDS PLL Design

  • Designed the GPLL & LVDS PLL in the APEX-II 2A70 (First Altera device in 130nm Cu).
  • Optimized the LVDS PLL to exceed 1GHz with the lowest jitter in the APEX-II family.
  • Achieved first silicon success for both GPLL and LVDS PLL.

VLSI Mask Design and Development

  • Floor-planned and optimized layout modules to minimize die size and maximize performance.
  • Debugged DRC and LVS violations and enhanced layout verification flows.

Design and Integration of Telecommunication Systems.

  • Radio communication systems for buildings, offshore petroleum platforms, car parks and tunnels.
  • CDMA Wireless Local Loop System for Klang Valley, Malaysia.

Core member of the CTO office in Altera.


Proficient in spoken and written English, Mandarin, Cantonese and Malay.

B. Sc: Electrical Engineering, Expected in 1996
Wichita State University - Wichita, Kansas
GPA: GPA: 3.907 / 4.000

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