Senior Electrical Engineer with 12 years of experience in IP development and validation. Versed in the broad areas of Hardware platforms, Pre-Silicon emulation, and Post-Silicon system & electrical validation.
Platforms: Win OS, Win Mobile, Linux OS, MicroC/OS-II (MPC 860)
Languages: C/C++, Assembly (x86, ADSP), Verilog HDL, Python and Linux Shell scripting
HW Tools: Oscilloscope, Logic analyzer, ITP, JBERT, AWG, Cadence Allegro, VNA, TDR
SW Tools: LogicWorks, Verilogger Pro, MathLab, LabVIEW
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