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Assistant System Engineer Resume Example

Resume Score: 55%

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ASSISTANT SYSTEM ENGINEER
Accomplishments
  • Effect of MOS Capacitance, CV characteristics, Threshold Voltage Adjustment in MOSFET devices using Silvaco Atlas.
  • Simulation of MOS capacitance is performed on Silvaco Altas software.
  • CV characteristics of MOFET with ideal and non-ideal threshold voltages were studied.
  • Calculated non ideal threshold voltage and simulated threshold voltage is verified.
  • The effect of flat band voltage, semiconductor potential, electric field and band bending in accumulation, depletion and inversion mode are studied.
  • Bulk FinFET Simulation using Silvaco Athena and Atlas Tools Process Steps involved in manufacturing Bulk FinFETS and its device characteristics such as threshold voltage, Subthreshold swing and CV characteristics are simulated and studied using Slivaco Athena and Atlas tools.
  • Double Patterning, replacement metal gate, the effects of fin height, fin width is also studied and simulated.
  • Sub-Micron and Advance Sub-Micron CMOS Processing and Fabrication.
  • CMOS devices with channel lengths of 1.0 um and 0.5 um is fabricated using Sub- CMOS and ADV Sub- CMOS process technologies.
  • MESA tool (database for the process flow) is used while fabricating the devices.
  • Different process like RCA clean, Oxidation, Lithography, Etching, Ion Implantation, Sputtering are performed.
  • Electrical testing is performed to verify the I-V characteristics, threshold voltage subthreshold swing, trans conductance.
  • Aluminum Deposition using Physical Vapor Deposition Aluminum is deposited on glass slide using PVD evaporator.
  • The deposition is performed on two different glass substrate placed at different distances from source.
  • The thickness of aluminum film is measured by surface profilometer and 4-point probe.
  • The thickness of the film is observed to be higher for the substrate placed closer to the source than the substrate place farther.
  • It is observed that the non-uniformity of the film formed on the farther substrate is less as compared to the closer substrate.
  • Modeling the suitability and applicability of Ultra capacitors on regenerative braking and powering of electric cars Project aims at powering the electric cars smartly by using Ultra-capacitor in hybrid combination of batteries.
  • Buck Boost Circuit was used in the project.
  • Boost Circuit Supply Power from Ultra-Capacitor and battery while acceleration of car.
  • Buck circuit supply power back to the Ultra Capacitor and Battery while braking.
  • A microcontroller based circuit was design that critically manage the switching between the buck and boost circuit.
Professional Summary
. Graduate student seeking for Job in the field of Integrated Electronics or Microelectronics Fabrication
Skills
    Cadence Virtuoso and Spectre, Mentor Graphics Pyxis,Silvaco, Matlab, SAP ERP, SAP Crystal Reports, Informatica, PL-SQL, Oracle 11g, C Language, Assembly Language, Keil uversion 3.
  • Linux and Unix specialist
  • Time management
  • Semiconductor process system
  • Skilled with analytical software
Work History
Assistant System Engineer, 02/2014 to 07/2014
Company Name – City
  • 17Gb/s, 60GHz OOK Transceivers design in 45nm CMOS for Inter- and Intra-Chip wireless communication.
  • LNA: - Designed 2 Stage LNA in 45nm technology using Cadence Virtuoso and Spectre.
  • The circuit is optimized to achieve gain of 28dB, 3dB bandwidth of 17GHz, Noise Figure of 2.8 dB, power consumption of 3.58mW and supply voltage of 1V.
  • Envelop Detector: -Designed envelop detector consist of source degenerated differential amplifier at the input stage of envelop detector and two-stage buffer amplifier at the output.
  • The circuit is optimized to achieve gain of 16dB, maximum data rate of 17Gb/s.
  • Academic Projects Design and Simulation of Operational Amplifier at 1 Volt Power Supply using 45nm PDK in Cadence Virtuoso.
  • Schematic, Layout for the Operational Amplifier is designed in 45nm PDK in Cadence Virtuoso at 1 Volt power supply.
  • Differential amplifier is used with common source as second stage.
  • The total gain 55 dB with the Phase Margin of 54 degrees is obtained.
  • Circuit is simulated in different configuration to calculate PSRR, ICMR, OFFSET voltage, Output Rail to Rail Voltage.
  • Circuit found to be stable for variation in temperature, Corner analysis and Monte Carlo simulations are performed for 100 different temperature and voltage points.
  • Layout for the Operational Amplifier at 45nm was designed, DRC and LVS are cleared.
  • Multiplier based constant Gm current Reference -Multiplier based constant Gm current Reference current mirrors is implemented and verified using 45nm Technology (gpdk045) in Cadence Virtuoso.
  • The Calculations of width and length of the transistor are made in order to achieve current of 25uA at 1Volt supply, the value of Rset, sensitivity of current with the supply voltage and its sensitivity in open loop gain is studied and verified, the (W/L) of all the transistor are calculated, Corner Analysis, Monte Carlo analysis for 500 cases were performed and circuit is tested for different variations in the temperature.
  • PMOS, NOR and NAND gate design, Fabrication and electrical testing PMOS layouts are designed using Mentor graphics pyxis tool and the device fabricated on silicon n-type substrate, the device layouts include Resistors, PMOS, NOR gates, NAND gate.
  • The device was fabricated using the standard processing steps such as Oxidation, Etching, Lithography, ion implantation, sputtering.
  • Silvaco Athena and Atlas software tools are used to predict the geometrical properties and material properties of semiconductor devices, Electrical Testing is performed, the I-V characteristics are studied.

Education
Master of Science: Electrical Engineering, Current
Rochester Institute of Technology - City
Electrical Engineering 3.2/4 Relevant Courses - Microelectronics Fabrication, Semiconductor Process Modeling, CMOS Manufacturing, Fundamentals of MEMS, Thin Films, Analog Devices
Bachelor of Engineering: Electronics Engineering, G.H. Raisoni College of Engineering CGPA -
Electronics Engineering 7.46/10
Network theory, Electronics Devices and Circuits, Digital Circuits, Power Electronics, Linear Electronics, Control Systems, Programming language C and Data Structure, Computer Architecture, Digital Communication, Microprocessors.:
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Resume Overview

School Attended

  • Rochester Institute of Technology
  • G.H. Raisoni College of Engineering CGPA

Job Titles Held:

  • Assistant System Engineer

Degrees

  • Master of Science : Electrical Engineering , Current
    Bachelor of Engineering : Electronics Engineering ,
    Network theory, Electronics Devices and Circuits, Digital Circuits, Power Electronics, Linear Electronics, Control Systems, Programming language C and Data Structure, Computer Architecture, Digital Communication, Microprocessors. :

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