• Results‐oriented professional with over 20 years of intensive semiconductor experiences at top Foundries, Memory industries and Equipment Company, specializing on CMOS logic device, process integration development including unit process/tool technology solutions from various CMOS technology generations (0.25um planar transistor down to 5nm 3D FinFET).
• Provided leadership and direction through senior managers/engineers more than 10 years of progressive experience with strong skillets in building high-performance cross-functional teams and methodologies to consistently deliver timely results.
• High-energy device/process integration engineering leadership successful in building and motivating dynamic teams. And cultivates a company culture in which staff members feel comfortable voicing questions and concerns, as well as contributing new ideas that drive technology solutions of advanced CMOS logic development and volume production.
• Semiconductor device/integration expertise of various semiconductor generations across Planar, 3D FinFET and GAA unit process, full integration and device technology.
• Executed the transistor roadmap definition and its inflections of upcoming & future technology, anticipating future needs and directing the technology development path of new approaches.
• Leadership in technology development for delivering innovative technology solutions & validating product development paths by leading FEOL/MEOL transistor technology team across multiple technology nodes including scaled FinFETs(10nm/7nm/5nm) and future GAA CMOS logic.
• Proven track record of advance CMOS logic device technology development and mass production set-up for fast yield ramp-up activity for high volume products of various technology generations including from poly/Si to hi-k/metal gate as well as embedded Flash CMOS logic technologies.
• Device technical lead for all aspects of core/SRAM/IO/Passive device development of advanced CMOS technologies interacting with marketing/benchmarking groups in order to define technology requirements and parametric goals for technology roadmaps specializing on device electrical targeting/process development & optimization by working closely with unit process, process integration and modeling team to ensure high quality spice model development for each technology requirement across various technology generations.
• Accomplished technical device & integration lead/manager with extensive experience in leading-edge silicon transistor technology development and volume productions including 180/150/65/45nm Poly/SiON and 32/28/20nm high-K metal gate low-power & high performance devices and their customer-based technologies.
• Device & integration engineering leadership roles across various industries – Applied Materials, GLOBALFOUNDRIES(+IBM-Alliance), SSMC and SK-Hynix, brining strong semiconductor industrial experiences; good understanding in unit process, process integration, device physics, core/IO/SRAM/Passive device design, device reliability and process optimization for the successful technology research & development and transferring to volume production.
• Authored and co-authored above 50 research and development papers in international journals and conferences, including more than 30 patents issued for innovation in the field of semiconductor unit progress, integration and devices.
US Permanent Resident
• Executed the definition of transistor roadmap, its inflections of upcoming & future technology and the validation of product pathway solutions by leading FEOL/MOL advanced Transistor Technology Team
• Participated internal technology forum, top account alignment and various top customer technical meetings and engaging regular interlock with customers' customers to improve product positions by sensing technology challenges & High Value Problems (HVP)
• Managed & directed process technology groups responsible for research, development and implementation in new products and extensions or enhancements to existing product lines
• Interacted and offered solutions to address external customers unusually complex process issues to address customers HVP involving the business unit's product line
• Actively participated in strategic planning to integrate research and development processes with both the unit and the Product Business Group's overall business plan across broad product portfolios
• Developed innovative solutions & validating product development paths with cross-functional teams utilizing various test vehicles for N+1/N+2 & beyond, including FinFET &GAA(Nano-wire ad Nano-sheet) transistors
• Took lead for pathfinding research works on alternative & energy efficient new switches including Ferroelectric based-FETs, 2D-TMD, IGZO channel devices as well as disruptive technology team in vetting 2D materials, selective metals, NCFET driving university programs for new materials/chemistry
• Drove & executed logic transistor road-map definition of N+1/N+2 & beyond, its inflections of upcoming & future technology for new channel materials and new architectures(scaled Si/SiGe FinFET, Gate-all-around(GAA)), including identification of the process integration challenges and requirements as well as delivering the superior results that generate value and fuel growth knowledge through internal and external benchmarks and shared knowledge to set high standards, drive speed and continuous improvement and maintain competitive technology leadership
• Participated in regular technology review meetings & provide key technology solutions to influence the customer technology roadmap
• Took lead of pathfinding activities for various technology solutions to meet PPAC(power/performance/area/cost) across key modules such as STI/Fin, Metal Gate stack, Spacer & S/D-Epi Junction and contact/MOL processes in scaled FinFET technology, delivering the winning solutions to various industries
• Developed GAA technology process by leading joint-development with IMEC and successfully developed various module solutions of scaled FinFET(Si/SiGe channels) highlighting defect-free SiGe channel, thin film band-edge WF metals, highly-doped Epitaxial S/D junction, innovative contact processes for meeting next generation contact resistance requirements
• Led and drove a multi-module process team to set up advanced 3D transistor (FinFET) test vehicles(SADP/SAQP Fin patterning) which are being fully utilized to evaluate new products and process integration solutions
• Device lead of 10nm FinFET technology development, responsible for all aspects of core/SRAM/IO/Passive device development interacting with marketing/benchmarking groups in order to define competitive technology power/performance target and parametric goals/electrical target definition with TCAD/modeling teams.
• Actively involving for intensive technical discussion/review of key process elements including Fin patterning, Fin width/height profile optimization, low-k spacer, innovative S/D epi-junction as well as multi-WF engineering.
• Participating in design rule as well as process architecture definition across key modules in terms of device viewpoints.
• Closely working together across functional teams (Process Integration/Unit modules/TCAD/modeling/performance benchmarking) by driving technology solutions to meet 10nm technology requirements.
• Leading device testing macro development (modeling and DOE macros) of 10nm FinFET device/process learning, including macro contents definition and macro layout with pcells in Cadence.
• Managed 20nm device team of 25 of professionals, responsible for leading device team to drive 20nm high-k/metal gate technology solutions, including planning/executing/validating device performance step-up process elements and their implementation to meet technology requirements and customer needs for their products. Leading of the device performance task force and coordinating the joint efforts between Integration/Device/SRAM /TCAD and modeling teams, delivering the clear outcomes/direction to drive the solutions.
• Took lead of device performance step-up plan/execution focusing on S/D junction (SMT+epi SiP and eSiGe) and RMG module process upgrade to deliver customer product yield and reliability requirement by defining full technology solutions.
• A seamless interface role between unit process module, integration, device and modeling team in terms of device maturity learning to meet technology milestones and customer product requirements.
• Provided the process run paths for customer products with spice model to hardware correlation validation to meet customer's requirement by running regular customer interlock meetings- face to face and conference calls.
• Coaches and mentors engineers/staffs in device team, influencing and encouraging engineers to fulfill their tasks in timely manner. And, actively engages in discussions and participates in and leads cross-functional teams across sites.
• Managed 20nm device team of 15 of professionals towards the end of the development cycle to ensure a smooth transition and handoff to the manufacturing teams.
• Successfully built and led team to drive 20nm high-k/metal gate technology development program, validating device performance step-up process elements and their implementation for baseline process upgrade to deliver SRAM yield as well as reliability requirements.
• Developed overall device improvement road map and successfully executed the plan for device performance step-up to meet the technology requirements as well as customers' needs across all devices - core/IO/SRAM/Passive devices, working closely with reliability counterpart to ensure the device meets all customer reliability targets.
• Worked daily base with FEOL Integration Team to ensure the appropriate experiments to explore options to enhance transistor characteristics and puts in place the tools and infrastructure to measure and evaluate the experiments when they are completed.
• Participated in the process change control procedure along with their integration counterparts and will help establish device electrical monitors, targets and appropriate controls and disposition criteria to ensure quality and reliability.
• Designed and developed CMOS logic and SRAM devices of 20nm metal gate/high-k(RMG) technology, including 20nm device target definition and device performance stepup, early customer engagement interactions, technology transferred back to home Fab(Malta Fab8, GlobalFoundries) and ensured that SRAM device specifications for performance, leakage and yield were met as 20nm SRAM device owner.
• Accomplished for all aspects of core/SRAM/IO/Passive device development of advanced 20nm RMG CMOS technology interacting with marketing/benchmarking teams in order to define technology requirements and parametric goals for technology road maps specializing on device electrical targeting/process optimization by working closely with process integration and modeling groups to ensure high quality spice model development.
• Device lead of advanced 28LP MG/HK CMOS logic technology development for early customer engagement activity across all devices - core/IO/SRAM/Passive devices on 28nm hi-k/metal gate low power customer needs as well as customized device design and development for device maturity and transferred back to home fab(Fab1, Dresden in Germany) for volume production.
• Actively participated in intensive & open discussion with multiple teams under JDA to drive the technical issues for clear and right decision making so as to move forward with high confidence level.
• Kept providing the relevant guidance to junior engineers to see the right direction on problem definition as well as fix solution on technical issues.
• Development of 32/28nm high-k/metal gate low power technology focusing on logic and ultra-dense SRAM cell device architecture design in a joint development with the ISDA 32/28nm Bulk alliance partners in IBM East-Fishkill, NY. Successfully logic device performance step-up plan/execution as well as SRAM device/Yield (Vmin)/leakage improvement activities across cross-functional teams.
• Played a key role on device performance step-up & optimization under key process upgrades - new cSiGe, Spacer, Junction and gate stack engineering to meet core device performance(DC/AC) and SRAM Iread/Istby as well as Vt-mismatch on target including successful completion of FEOL reliability qualification, PDK delivery and SRAM stress closure.
• Help identified key process elements on metal gate work function control as well as device variability sources of 32/28LP HK/MG development floor and successful implementations as baseline process, including innovative device design to co-optimize stress and high-k dielectric performance, stress memorization engineering.
• Intensive bench testing and characterization by solving on HKMG unique device issues: Vt/mobility temperature dependence, AC Reff, local layout effects with n/p-metal boundary effects. Various device variability sources identified and implemented mitigation solutions from Poly/SioN tech to HK/MG tech (32/28nm) nodes.
• Actively involved for development of SRAM bit cells, SRAM device electrical targeting & development/characterization of the cells (e.g. static noise margin, Iread, Icrit, retention) and analysis of SRAM functionality & parametric data bridging into SRAM yield engineering activity specializing on device mismatch(Avt) improvement and execution to meet technology Vmin requirement for low leakage and performance SRAM cell families.
• Successfully developed and transferred customized 65/45nm CMOS logic low power and high performance technologies for volume production with identification and validation of a novel process schemes to achieve device performance target as well as the lowest standby leakage with high enough performance in dense SRAM cell.
• One of the key drivers for the success of 65nm low power technology (Alliance project-IBM/Samsung/Chartered), followed by the extension to the successful completion with several key customer engagement for their volume production by meeting overall requirements for Logic and SRAM device characteristics, resulting in superior product yield demonstration to meet Iddq vs Fmax requirement.
• Made significant contribution to 45nm low power SRAM device development which met Iread/Istby target, dramatic Vmin improvement by SRAM cell device optimization as well as device variability reduction by initiating Carbon-co implantation introduction as baseline process.
• Research & developed for 0.25um RF CMOS and transferred to mass production, including SPICE matching activity and driving technology solutions on critical device issues (INWE, double hump & Idlin degradation).
• Successfully executed prototyping management and device/process improvement for fast yield ramp-up of a high volume of logic products including embedded Flash/SRAM devices by working closely with unit process and yield engineering team focusing on device/process analysis & characterization.
• Led technology qualification activities for release for production of logic & embedded flash memory products of 0.14/0.15/0.18/0.25um technologies by driving technology solutions on technical challenges based on solid semiconductor device physics & device parametric knowledge covering manual bench failure analysis and characterization.
• Device characterization for advanced CMOS devices including embedded Flash/SRAM: Electrical targeting/SPICE model matching, programming/erasing window, mobility, charge trapping, interface states, leakages and SRAM functionality incl. stability & read/write margin analysis as well as device parameter targeting to meet specific logic and SRAM bitcell performance(Vmin).
• Developed the 0.14um Embedded Flash Memory technologies in SSMC with cooperation with Philips Semiconductor (now, NXP), prototype-supporting and leading process improvement team such as photo evaluation, 0.14um CMOS flash and logic device optimization to obtain the robust process margin for mass production.
• Successfully transferred 0.15/0.18um CMOS logic and 0.15um Embedded Flash Memory technologies from Philips Semiconductor to SSMC, qualified for release for production and prototyping management and yield improvement of embedded flash products as a process owner for 0.15um flash memory devices.
• One of key members in the team working in development and manufacturing for various generation SDRAM technologies that included research and development as well as yield improvement by logic device and DRAM cell engineering.
• Played key device/Integration interface role in one of Blue Chip Projects, 128M & 256M-DDR SDRAM (0.16um technology) research & development and successfully transferred mass production.
• Specialized in DRAM cell engineering to meet retention time requirement from various process improvement with innovate memory cell junction/capacitor) engineering through DOE and TCAD simulation work.
• Developed 256M-SDRAM using 0.15um technology (using Metal Gate & Ta2O5 Capacitor technology) in terms of optimization of memory cell transistor and retention time improvement.
• Successfully completed memory Cell engineering across gate/junction modules to meet technology requirement from in-depth device reliability characteristics (HCI & TDDB) depends on the in-line process of each product.
• Key device/process integrator of 5th-64M(0.20um technology) & 3rd-128M-SDRAM(0.18um technology) Research & Development and transferred mass production
• New DRAM Cell & Periphery circuits' device development and mass production set up of specializing in Test pattern (Macros) design and TCAD simulation using OPUS tool, SUPREM4 & MEDICI simulators and in-depth device electrical analysis by various measurement bench testing equipment.
• Retention time engineering (Pause and Disturbance) in DRAM memory cells including device reliability evaluation (HCI & TDDB).
• Managed electrical analysis for device development on 2nd-64M-SDRAM (0.20um technology) cell engineering and development and yield improvement in high volume FAB during the period of development and mass production set up.
• Device engineering (cell and periphery transistors), design rule generation, mask tooling and process quality control of entire integration process.
• Technical staff managing/leadership skills with cross-functional team management to drive technology solutions
• Project/Task force team management skills as complex problem solver and strong decision maker
• Strategy planning & execution skills of business unit to drive the assigned goals
• Strong team player with technical leadership and teamwork across functional teams to identify process integration challenges and solutions for advanced logic technologies with embedded memory technologies
• Good knowledge and skillsets for advanced logic technology road-map definition, its inflections of upcoming & future technologies including scaled FinFET, GAA and alternative new switches- Ferroelectric based negative capacitance-FETs, 2D-TMD, IGZO channel devices
• Semiconductor unit process, full integration process and device design/characterization/modeling in the advanced CMOS technology development from poly/Si to hi-k/metal gate(gate first/gate last schemes) including logic(Planner/3D FinFET/GAA) and memory devices
• Equipped with strong device analytical skills and process integration knowledges to meet each technology performance/leakage power requirements as per customer needs
• Nano-scale solid-state electronic device design and development including application of new materials and new structures to transistors for deeply scaled devices including metal gate eWF tuning, Source/Drain junction engineering with epitaxial growing - SMT+eSiP/eSiGe for performance boosting
• Thorough knowledge & development skills on all aspects of devices - Core/IO/SRAM/Passive device design of CMOS logic as well as embedded memory devices such as SRAM, DRAM and Flash/EEPROM memory
• Fundamental & broad knowledges of semiconductor processing (Litho, ALD, CVD, PVD, RIE, CMP, IMPLAT & Anneals) across FEOL/MEOL of advanced logic technologies including planner & 3D FinFET/GAA
• Process integration induced physical film characterization and analysis (AFM, SEM, TEM, EDX, XRD, Raman, Auger, etc.)
• Familiarity with data analysis software such as SAS, Dataview, JMP, Cornerstone, Datapower for in-depth device analysis/ characterization.
• Scribe test structure layout, electrical testing and characterization as well as Cadence Layout tools for structure verification & TCAD tools(medici, tsuprem & Taurus workbench), bench characterization utilizing device characterization tools as well as equipment: S300 Cascade Microtech semi-auto probe station, HP4156B Semiconductor Parameter Analyzer, Capacitance meters, etc.
1. SSMC 1st award of CIT (continuous Improvement Team) project as a process owner, “ Introduction of 1st time product using 0.15um embedded Flash memory device” in 2004, Philips QIC winner for regional final of Asia and participation of QIC World final for Philips Semiconductor in Apr, 2005
2. Award of “One Million Dollars” Project 2005 in SSMC of Singapore
3. “STAR” Award from 2005 NIQC in SSMC of Singapore
4. Recognition Award of 64M/128M/256M SDRAM Development and successful mass production set-up in Hynix Semiconductor of South Korea
56. Toshihiko Miyashita, Shiyu Sun, Sushant Mittal, Myung Sun Kim, Ashish Pal, Angada Sachid, Kalpana Pathak, Matt Cogorno, and Nam Sung Kim, “Selective Fin Trimming after Dummy Gate Removal as the Local Fin Width Scaling Approach for N5 and Beyond”, IEDM 2018
55. R. Ritzenthaler, H. Mertens, V. Pena, G. Santoro, A. Chasin, K. Kenis, K. Devriendt, G. Mannaert, H. Dekkers, A. Dangol, Y. Lin, S. Sun, Z.Chen, M. Kim, J. Machillot, J. Mitard, N. Yoshida, N. Kim, “Vertically Stacked Gate-All-Around Si Nanowire CMOS Transistors with Reduced Vertical Nanowires Separation, New Work Function Metal Gate Solutions, and DC/AC Performance Optimization”, IEDM 2018
54. G. Hellings, H. Mertens, A. Subirats, E. Simoen, T. Schram, L.-A. Ragnarsson, M. Simicic, S-H. Chen, B. Parvais, D. Boudier, B. Cretu, J. Machillot, V. Pena, S. Sun, N. Yoshida, N. Kim, et al., “Challenges for I/O Towards The 3-nm Node: Si/SiGe Superlatttice I/O FinFET in a Horizontal Nanowire Technology and The Increased Susceptibility of Bulk FF Technology to Single Event Latchup”, 2018 Taiwan ESD and Reliability Conference
53. Jong Youn Choi, Christopher F.Ahles, Raymond Hung, Namsung Kim, et al., “Selective atomic layer deposition of MoSix on Si (001) in preference to Silicon Nitride and Silicon Oxide”, Applied Surface Science 2018
52. Jong Youn Choi, Christopher F.Ahles, Raymond Hung, Namsung Kim, et al., “Selective Atomic Layer Deposition of MoSix on Si (001) in Preference to Silicon Nitride and Silicon Oxide”, Materials Research Society (MRS) 2018
51. P. Blaise, B. Sklénard, N. Vaxelaire, O. Renault, T. Miyashita, K. Wong, and N. Kim, “Understanding Ferroelectricity of doped-HfO2 for the NC-FET”, Semiconductor Interface Specialists Conference 2018
50. C. F. Ahles, J. Y. Choi, R. Hung, N. Kim, et al., “Selective Etching of Native Silicon Oxide and Flowable SiO2 in Preference to Silicon, Thermal Silicon Oxide and Silicon Nitride”, Semiconductor Interface Specialists Conference 2018
49. G. Hellings, H. Mertens, A. Subirats, E. Simoen, T. Schram, L.-A. Ragnarsson, M. Simicic, S-H. Chen, B. Parvais, D. Boudier, B. Cretu, J. Machillot, V. Pena, S. Sun, N. Yoshida, N. Kim, et al., “Si/SiGe Superlattice I/O FinFETs in a Vertically-Stacked Gate-All-Around Horizontal Nanowire Technology”, VLSI Technology 2018
48. Namsung Kim, “Transistor Scaling Challenges and Opportunities to Pave for the Single-Digit Technology Node (Invited)”, Semicon Korea 2018
47. Raymond Hung, Jin Hee Park, Tae Hong Ha, Mark Lee, Wenting Hou, Jianxin Lei, Jonathan R. Bakke, Shashank Sharma, Karthik Raman Sharma, Amir Wachs, Namsung Kim, et al., “Extreme Contact Scaling with Advanced Metallization of Cobalt”, International Interconnect Technology Conference(IITC) 2018
46. Raymond Hung, Fareen Adeni Khaja, Kelly E Hollar, KV Rao, Samuel Munnangi, Yongmei Chen, Motoya Okazaki, Yi-Chiau Huang, Xuebin Li, Hua Chung, Osbert Chan, Christopher Lazik, Miao Jin, Hongwen Zhou, Abhilash Mayur, Namsung Kim, et al., "Novel Solutions to Enable Contact Resistivity <1e-9 w-cm2="" for="" 5nm="" node="" and="" beyond",="" international="" symposium="" on="" vlsi="" technology,="" systems="" and="" application(vlsi-tsa)="">1e-9>
45. H. Mertens, R. Ritzenthaler, V. Pena, G. Santoro, K. Kenis, A. Schulze, E. D. Litta, S. A. Chew, K. Devriendt, T. Chiarella, S. Demuynck, D. Yakimets, D. Jang, A. Spessot, G. Eneman, A. Dangol, P. Lagrain, H. Bender, S. Sun, M. Korolik, D. Kioussis, M. Kim, K-.H. Bu, S. C. Chen, M. Cogorno, J. Devrajan, J. Machillot, N. Yoshida, N. Kim, et al., "Vertically Stacked Gate-All-Around Si Nanowire Transistors: Key Process Optimizations and Ring Oscillator Demonstration". IEDM 2017
44. N. Yoshida, S. Hassan, W. Tang, Y. Yang, W. Zheng, M-.S. Chen, L. Dong, H. Wang, M. Jin, M. Okazaki, J. Park, N. Bekiaris, R. Hung, Y. Lei, P. Ma, X. Tang, T. Miyashita, N. Kim, et al., "Highly Conductive Metal Gate Fill Integration Solution for Extremely Scaled RMG Stack for 5 nm & Beyond", IEDM 2017
43. Raymond Hung, Jin Hee Park, Tae Hong Ha, Mark Lee, Wenting Hou, Jianxin Lei, Jonathan Bakke, Shashank Sharma, Hans Gossmann, Miao Jin and Nam Sung Kim, "Advanced Contact Metallization with Void-Free Cobalt Fill", Advanced Metallization Conference 2017
42. Jong Youn Choi, Christopher Ahles, Raymond Hung, Namsung Kim, et al., "Selective atomic layer deposition of MoSix on Si (001) in preference to Silicon Nitride and Silicon Oxide", 48th IEEE Semiconductor Interface Specialists Conference, 2017
41. Chih-Yang Chang, Fareen Adeni Khaja, Kelly E Hollar, KV Rao1, Christopher Lazik, Miao Jin, Hongwen Zhou, Raymond Hung, Yi-Chiau Huang, Hua Chung, Abhilash Mayur, Namsung Kim, "Ultra-low (1.2×10−9 Ωcm2) p-Si0.55Ge0.45 contact resistivity (ρc) using nanosecond laser anneal for 7nm nodes and beyond", 2017 17th International Workshop on Junction Technology (IWJT)
40. C.-N. Ni, S. Jun, A. Vyas, F. Khaja, K.V. Rao, S. Sharma, M. Jin, C. Lazik, A. Mayur, J. Gelatos, H. Chung, R. Hung, N. Yoshida, N. Kim, "PMOS contact resistance solution compatible to CMOS integration for 7 nm node and beyond", 2016 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)
39. C.-N. Ni, K.V. Rao, F. Khaja, S. Sharma, S. Tang, J. J. Chen, K. E. Hollar, N. Breil, X. Li, M. Jin, C. Lazik, J. Lee, H. Maynard, N. Variam, A. J. Mayur, S. Kim, H. Chung, M. Chudzik, R. Hung, N. Yoshida, N. Kim, "Ultra-low NMOS contact resistivity using a novel plasma-based DSS implant and laser anneal for post 7 nm nodes", 2016 IEEE Symposium on VLSI Technology
38. Sameer H. Jain1, H.Shang, N.S.Kim, et al., “Device challenges for High Performance Bulk Planar 20nm CMOS Technology”, SEMI China 2013
37. Huiling Shang, S. Jain, E. Josse, E. Alptekin, M.H. Nam, S.W. Kim, K.H. Cho, I. Kim, Y. Liu, X. Yang, X. Wu, J. Ciavatti, N.S. Kim, et al., “High Performance Bulk Planar 20nm CMOS Technology for Low Power Mobile Applications”, 2012 Symposium on VLSI Technology Digest of Technical Papers
36. M. Hamaguchi, D. Nair, D. Jaeger, H. Nishimura, W. Li, M-H. Na, C. Bernicot, J. Liang, K. Stahrenberg, K. Kim, M. Eller, K-C. Lee, T. Iwamoto, Y-W. Teh, S. Mori, Y. Takasu, JH Park, L. Song, N-S. Kim, et al., “New Layout Dependency in High-K/Metal Gate MOSFETs”, Electron Devices Meeting (IEDM), 2011
35. Jin-Ping Han, Takashi Shimizu, Li-Hong Pan, Moritz Voelker, Nam Sung Kim, et al., “Novel High-Performance Analog Devices for Advanced Low-Power High-k Metal Gate Complementary Metal–Oxide–Semiconductor Technology”, Japanese Journal of Applied Physics 50 (2011)
34. J.-P. Han, T. Shimizu, L. H. Pan, M. Voelker, C. Bernicot, F. Arnaud, A. C. Mocuta, K. Stahrenberg, N. Kim, et al.“Cost Efficient Novel High Performance Analog Devices Integrated with Advanced HKMG Scheme for 28nm CMOS Technology and Beyond, the 42nd International Conference on Solid State Devices and Materials 2010
33. F.Arnaud, A.Thean, M.Eller, M.Lipinski, Y.W.Teh, M.Ostermayr, K.Kang, N.S.Kim, et al., “Competitive and Cost Effective high-k based 28nm CMOS Technology for Low Power Applications”, Electron Devices Meeting, 2009. IEDM 2009. IEEE International, 7-9 Dec. 2009 Page(s): 651-654
32. Nam Sung Kim, et al., “SRAM Variability: Foundry Perspectives - Understanding of SRAM Variability and Implications on Bitcell Performance (Invited)”, NMI 2nd International Conference on CMOS Variability: ICCV 2009
31. D.-G. Park, K. Stein, K. Schruefer, Y. Lee, J.-P. Han, W. Li, H. Yin, C. Pacha, N. Kim,“ High-/Metal Gate Low Power Bulk Technology - Performance Evaluation of Standard CMOS Logic Circuits, Microprocessor Critical Path Replicas, and SRAM for 45nm and beyond”, 16th International Symposium on VLSI Technology, Systems and Applications (2009 VLSI-TSA) from 27 to 29 April 2009
30. Yang, H.S. Wong, R. Hasumi, R. Gao, Y. Kim, N.S. et al., “Scaling of 32nm Low Power SRAM with High-K Metal Gate”, Electron Devices Meeting, 2008. IEDM 2008. IEEE International, 15-17 Dec. 2008 Page(s): 233-236
29. X. Chen, S. Samavedam1, V. Narayanan, K. Stein, C. Hobbs1, C. Baiocco, W. Li, D. Jaeger, M. Zaleski1, H. S. Yang, N. Kim, et al., “A Cost Effective 32nm High-K/ Metal Gate CMOS Technology for Low Power Applications with Single-Metal/Gate-First Process”, VLSI Technology 2008
28. Young Seon You, Nam Sung Kim, et al., “Investigation on Metal Pillar Defect in sub-micron CMOS technology”, Semiconductor Manufacturing, 2006. ISSM 2006, IEEE International Symposium
27. Young Seon You, Nam Sung Kim, et al., “Impact on Off-state Leakage Current in PMOS Device by Metallic Contamination” Semiconductor Manufacturing, 2006. ISSM 2006, IEEE International Symposium
26. Nam Sung Kim, et al., “Effect of Ti-rich TiN as a Co-salicide capping layer for 0.15 um embedded flash memory devices and beyond” Thin Solid Films, Volume 504, Issues 1-2, 10 May 2006, Pages 20-24
25. Kyeong Sik Lee, Nam Sung Kim, et al., “Impact of untreated thicker CVD TiN film at a Via glue layer on Rc Performance in 0.15um CMOS Technology”, Reliability Physics Symposium Proceedings, 2006. 44th Annual. 2006 IEEE International
24. Sang Hyun Han, Dong Ju Son, Nam Sung Kim, et al., “Control gate-bit line leakage induced cobalt silicide migration in 0.15um embedded flash memory devices”, Non-Volatile Memory Technology Symposium, 2005 7-10 Nov. 2005 Page(s): 25 – 30
23. Jing Zhao, Nam Sung Kim, et al., “A new low temperature APM cleaning process to improve ONO integrity in 0.18 m stacked-gate EEPROM memory”, SSDM 2005
22. Nam Sung Kim, et al., “Effect of Checker Board Failure on Yield improvement in 0.15um Embedded Flash Memory” Semiconductor Manufacturing, 2005. ISSM 2005, IEEE International Symposium on 13-15 Sept. 2005 Page(s): 237-240
21. Nam Sung Kim, et al., “Effect of Ti-rich TiN as a Co-salicide Capping Layer for 0.15um Embedded Flash Memory Devices and Beyond” ICMAT 2005 & IUMRS-ICAM 2005 in Singapore
20. Nam Sung Kim, et al., “Successful Fault Isolation of Bit Line Leakage and Leakage Suppression by ILD Optimization in Embedded Flash Memory” 12th International Symposium on the Physical and Failure Analysis of Integrated Circuits 2005
19. Sang Hyun Han, Nam-Sung Kim, et al., “Reliability Failure induced by the Si Epitaxy Growth on PMOS High Voltage in 0.15um Embedded Flash Memory Devices” Non-Volatile Memory Conference, 2004
18. Nam-Sung Kim, et al., “Impact of Co-salicide capping layer on GIDL in High Voltage devices for Embedded Flash memory” SSDM(Solid State Devices and Materials) in Japan, 2004
17. Nam-Sung Kim, et al., “Effect of Magnetic Field on Plasma Damage during VIA Etching in sub-micron CMOS technology” Reliability Physics Symposium Proceedings, 2004
16. Nam-Sung Kim, et al., “Impact of Ti Deposition and Subsequent RTA Process on Contact Resistivity Characteristics of W-Bit Line in Sub-Micron Dynamic Random Access Memory” Jpn. J. Appl. Phys. Vol. 42 (2003) 6784-6789, Part 1, No. 11
15. Il-Gweon Kim, Nam-Sung Kim, et al., “Reliability Degradation By Dynamic Operation Stress During Burn-In” Jpn. J. Appl. Phys. Vol. 42 (2003) 2091-2095, Part 1
14. Il-Gweon Kim, Nam-Sung Kim, et al., “Interlayer Dielectric (ILD)-Related Edge Channel Effect in High Density DRAM Cell” Electron Devices Meeting, 2002. IEDM '02. Digest. International, 8-11 Dec. 2002 Pages: 827 - 830
13. II.-G.Kim, N.-S.Kim, et al., “Improvement of Disturbance/Pause Retention Time by Reducing Edge Channel Effect of Cell in Gigabit Density DRAMs and Beyond” Solid State Devices and Materials in Japan, 2002.
12. J.-S.Park, S.-K.Choi, M.-J.Bong, S.-C.Chung, H.-C.Jung, N.-S.Kim, et al., “Suppression of Short Channel hump of nMOSFET Using NF3-Added ILD HDP process” Solid State Devices and Materials in Japan, 2002
11. N.-S.Kim, et al., “Impact of Ti Deposition Condition and Subsequent RTA on Contact Resistance of W-Bit Line in sub-micron technology DRAM” Solid State Devices and Materials in Japan, 2002
10. I.G-.Kim, J.-H.Chun, N.-S.Kim, et al., “Impact of Burn-In Stress on Reliability of High Density DRAMs” Solid State Devices and Materials in Japan, 2002
9. Nam-Sung Kim, et al., “Impact of Polymetal Gate Etch Post-Cleaning on Data Retention Time in Sub-micron DRAM Cells” Jpn. J. Appl. Phys.Vol.41
8. Il-Gweon Kim, Nam-Sung Kim, et al., “Low-Damage Gate Etching with High Degree of Anisotropy in High-Density DRAM Cell” Jpn. J. Appl. Phys.Vol.41, 2002
7. Il-Gweon Kim, Nam-Sung Kim, et al., "Real impact of W/WNx/Poly-Si gate stack in volume production of high density DRAM" Electron Devices Meeting, 2001
6. Kim D.-C., Park S.K., Hong H.S., Kim I.G., Kim Y.T., Kim Y.B., Kim H.S., Park H.S., Nam M.H., Suh M.S., Nam K.B., Lee J.S., Kim N.S., et al., "Impact of rapid thermal annealing on data retention time for 256 Mb and 1Gb DRAM technology” Electron Devices Meeting, 2001
5. N.-S. Kim, I.-G. Kim, et al., "Impact of Poly Metal Gate Etch Post-Cleaning on the Tail Distribution of DRAM Data Retention Time", Solid State Devices and Materials, Tokyo in Japan, 2001 Page(s):28-29
4. I.-G. Kim, J.-W. Bae, J.-H. Choy, N.-S. Kim, et al., "Impact of Gate Etch Damage and Profile in High Density DRAM Cell", Solid State Devices and Materials, Tokyo in Japan, 2001 Page(s):26-27
3. Kim Ilgweon, Kwon Jaesoon, Lee Kyosung, Kim Dongchan, Shin Jungho, Choy Junho, Kim Namsung, et al., "Retention time improvement by fast-pull and fast-cool (FPFC) ingot growing combined with proper arrangement of subsequent thermal budget for 0.18um DRAM cell and beyond" VLSI Technology, 2001. Digest of Technical Papers. 2001 Symposium on , 2001 Page(s): 125 –126
2. Nam-Sung Kim, Il-Gweon Kim, et al., "Optimization of n-junction through ion beam shadowing and buffering effect by tilt implantation with rotation for improving the retention time" Ion Implantation Technology, 2000.
1. Il-Gweon Kim, Nam-Sung Kim, et al., "Improvement of the tail component in retention time distribution using buffered n-implantation with tilt and rotation (BNITR) for 0.2 um DRAM cell and beyond" VLSI Technology, 2000.
Holds more than 20 registered patents
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