Results-driven Hardware Lead with a successful track record in leading/growing a team; developing test methodologies & plans to build highly reliable hardware systems.
Good communication skills with experience interacting with all types of Customers, Vendors and X-functional leads in a cooperative manner. Lead teams through multiple bring-ups and improved coverage, time or cost.
Adept at electrical and functional validation of High-Speed SERDES/IO interfaces. Skilled at building optimal test automation tools (HW/SW) for high throughput and to achieve dependable statistical metrics. Thorough understanding of IO char, Signal Integrity, SERDES, and functional testing.
Thesis titled: "Online and built-in self-testing techniques for Field Programmable Analog Array"
 Bonita Bhaskaran, Amit Sanghani, Kaushik Narayanun, Ayub Abdollahian, Amit Laknaur (Nvidia) Test Method and Scheme for Low-Power Validation in Modern SOC Integrated Circuits. VLSI Testing Symposium 2016 (VTS16').
 A. Laknaur, R. Xiao, and H. Wang “Design of a Window Comparator with Adaptive Error Threshold for Online Testing Applications,” International Symposium on Quality Electronic Design 2007(ISQED07'), has won Best Paper Award.
 A. Laknaur, R. Xiao, and H. Wang “A Programmable Window Comparator for Analog Online Testing,” VLSI Testing Symposium 2007 (VTS07').
 A. Laknaur, R. Xiao, and H. Wang “An Analog Checker with Programmable Adaptive Error Thresholds,” 2007 IEEE Instrumentation and Measurement Technology Conference IMTC07'
 A. Laknaur and H. Wang “A methodology to perform online self-testing for field programmable analog array circuits,” IEEE Transactions on Instrumentation and Measurement.
Resumes, and other information uploaded or provided by the user, are considered User Content governed by our Terms & Conditions. As such, it is not owned by us, and it is the user who retains ownership over such content.
Job Titles Held: