principal validation engineer resume example with 11 years of experience

Jessica Claire
  • Montgomery Street, San Francisco, CA 94105 609 Johnson Ave., 49204, Tulsa, OK
  • H: (555) 432-1000
  • C:
  • Date of Birth:
  • India:
  • :
  • single:
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Professional Summary

Results-driven Hardware Lead with a successful track record in leading/growing a team; developing test methodologies & plans to build highly reliable hardware systems.

Good communication skills with experience interacting with all types of Customers, Vendors and X-functional leads in a cooperative manner. Lead teams through multiple bring-ups and improved coverage, time or cost.

Adept at electrical and functional validation of High-Speed SERDES/IO interfaces. Skilled at building optimal test automation tools (HW/SW) for high throughput and to achieve dependable statistical metrics. Thorough understanding of IO char, Signal Integrity, SERDES, and functional testing.

Work History
Principal Validation Engineer, 11/2016 - 05/2019
Amgen Inc. Hackensack, NJ,
  • Worked towards the team goals for full DVT coverage for WIFI+Bluetooth combo chip programs
  • Debug and validation test plans and execution of functions and their co-ex stress and dependency analysis over PCIE PHY/link
  • Lead and implemented elaborate automation tools from scoping, planning, resource management and intuitive reporting with sorted charts and plots. This work resulted in high-efficiency tools for 1-Dual Function Stress testing tool and 2-Power consumption tool with 50+ rail debug capability
  • Worked with Analog designers to help explore BIST options like EOM
  • Test and Measurement Equipment evaluation and putting together an optimal configuration suiting over validation needs and constraints
Principal/Lead Validation Engineer, 09/2015 - 11/2016
Spectra7 Microsystems Inc. City, STATE,
  • Managed a technical team for all validation and debug efforts at module, functional and system level
  • Pre-sales customer (CM/OEM) facing product and validation demos
  • Documenting guides for each step of our chip integration into end products for the CM to build stronger confidence in our IP, support, & value
  • Lead Validation and Debug efforts with a small team of four: Develop test methodologies, automate and delegate tasks & priorities
  • Make cases for Equipment, man-hours and priorities to management
  • Provide customer support (CM) from IP to End User product development
Senior Mixed Signal Design Validation Engineer, 05/2011 - 09/2015
  • Characterization of the PCIE Gen1/2/3, Display Port, HDMI IO PHY and lead such validation efforts for different two GPU chip programs
  • Represented NVIDIA in MIPI CTS workgroups in its SPEC development efforts to keep us proactive in our design/test efforts
  • Scouting, evaluating, tailoring and purchasing of simulation and testing tools from different Vendors improving design workflow. Also includes the ROI discussion for funds approval.
  • Developed an in-house tool for clock characterization and power-noise measurement at ATE for DFT/PI testing, which sped up the flow by 50 times
Mixed Signal Design Validation Engineer, 04/2008 - 04/2011
  • Developed DSP tool (Matlab and Perl) to carry out the Electrical tests of Display interfaces (Display port, DVI, HDMI) which is also a cross functional effort
  • Represented NVIDIA in PCIE Gen3 test development with PCI-SIG in the test working group
  • Matlab scripts for Isolating Jitter components in signals and root causing noise source issues at macro and system level
  • Lead our group in a Chip bring-up (power-up) effort for Analog Validation
  • Characterization of the PCIE Gen1/2, DVI, MLS analog PHY and give feedback to the design team with findings to better next-generation designs and their testability
  • Processes building and Optimization
  • Test methodology and Test plan development
  • Data analysis to evaluate design strength
  • Efficient and systematic Test Automation tool development
  • Electrical, Functional, Stress testing
  • Leading from Work delegation to conflict resolution
  • Equipment, Lab and tool management
  • High-Speed SERDES / IO Design validation (PCIe, HDMI, DP InterChip links)
  • Oscilloscope, BERT, VNA
  • Semiconductor Device Physics, Signal Integrity, and DSP
  • Matlab, Perl, Allegro
  • OEM/CM Liason experience.
Ph.D.: Electrical & Computer Engineering, Expected in 08/2010
Southern Illinois University Carbondale - Carbondale, IL
Status -

Thesis titled: "Online and built-in self-testing techniques for Field Programmable Analog Array"

Master of Science: Electrical & Computer Engineering, Expected in 05/2005
Southern Illinois University Carbondale - Carbondale, IL
Status -
Bachelor of Engineering: Electrical, Electronics Engineering, Expected in 05/2003
Chaitanya Bharati Institute of Technology (CBIT), Osmania University - Hyderabad,
Status -
  • Designed a Comparator circuit with an adaptive error threshold and had been fabricated in a 0.18µm CMOS technology
  • Won Best Paper Award

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Resume Overview

School Attended

  • Southern Illinois University Carbondale
  • Southern Illinois University Carbondale
  • Chaitanya Bharati Institute of Technology (CBIT), Osmania University

Job Titles Held:

  • Principal Validation Engineer
  • Principal/Lead Validation Engineer
  • Senior Mixed Signal Design Validation Engineer
  • Mixed Signal Design Validation Engineer


  • Ph.D.
  • Master of Science
  • Bachelor of Engineering

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