Duration: 1 year ?
Duration 1 year
Tools: vcs [ Dynamic LP tool], Design Compiler, VC_STATIC
Languages: Verilog, VHDL, System Verilog
Power Format: CPF, UPF??
Duration 6 Months
Contributions: Worked as Trainee
Tools: IUS, CLP [ Dynamic and Static tool from Cadence] Languages: System Verilog.
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