Over 19 years experience in IC Manufacturing (Process and Development Engineering) and more than 5 years at Biotech Company. Developed and qualified Flip Chip Technology and QFN in IPAC and CORWIL. Extensive knowledge in Equipment Qualification considering IQ, OQ and PQ protocol. Hands-on Engineer and Program Manager. Published 7 patents and 4 already approved. Results oriented with track record of Project Development Phase (eg. meetings, evaluations, specs. and etc.) for easier turn over of deliverables. Skilled in QA tools, DOE and JMP software for statistical analysis and process control.
Auto CAD, Microsoft Works, Words, Excel, Power Point, Project, Visio, SAS Jmp, Camstar (MES), Trained in ISO 13485 .
Sr. MANUFACTURING ENGINEER September 2009 to CurrentPacific Biosciences Inc － Menlo Park, CA.
Responsible in equipment Qualification (IQ/OQ/PQ protocol), Sustaining and Maintenance.
Interface with cross functional team (eg.
QA, Safety, Product Development Engineer) to qualify and optimize new process equipment to support the Chip manufacturing for Single Molecule Real Time (SMRT) product.
Monitored Equipment Performance indices namely: MTBA and MTBF then identified areas of improvement.
Resolved internal equipment issues (eg.
Wet Bench, SRD, DATACON EVO Dispensing Equipment and etc.) and established short term and long term corrective action.
Interface with vendor during design phase to optimize equipment for HVM readiness.
Analyzed equipment data and initiated continuous improvement programs resulting to better equipment performance, operating cost and productivity and product quality.
Used six sigma, statistical process control and DOE, Interface with R&D to review requirement for New Product Introduction (NPI) to ensure proper transition to manufacturing.
Training and Mentoring engineers, technicians and operators.
SR. DEVELOPMENT ENGINEER / TPM September 2007 to May 2009Vertical Interconnect Inc － Scotts Valley, CA
Formulate timeline and provide directions in step by step qualifications of 3D 4Hi, 8Hi and 16Hi Stack Tier µSD LGA packaging.
Manage and interface cross-functional teams in the factory to achieve customer expectations.
Responsible in handling reliability requirements and assess failure analysis (SEM, EDX, Shadow Moire.
FTIR and etc.) Work with Engineering to oversee any potential design failures and provide assessment in mitigating the issue.
Ensure and reinforce implementations of Process Control Plans and address out of control condition in preparation for HVM mode.
Manage New Product Introduction (NPI) and ensure accurate package material and process requirement at specified timeline.
TECHNICAL PROGRAM MANAGER August 2005 to September 2007STATSChipPAC Inc － Fremont, CA
Responsible of providing directions of projects, design development and qualifications to the factory.
Manage or interface with cross- functional team (QA, Mfg, Eng., and etc.) for requirements or directions of new products.
Recommend optimum process solution on new products.
Work with Engineering and operations to oversee technical development, prototyping and testing on Flip Chip and BGA Packages.
Facilitate conflict resolution and escalate when necessary.
Create and manage program plans (Work breakdowns, Qualification build.
Reliability timeline, BOM preparation and etc.
PACKAGE DEVELOPMENT ENGINEER June 2003 to August 2005CORWIL TECHNOLOGY － San Jose, CA
Decided to move due to No family medical insurance) Developed and start-up Flip Chip Ball Grid Array (FCBGA).
Do material selection and equipment qualification.
Developed and start-up QFN package.
Support Precision Wafer Thinning Process.
Responsible to all Ball Grid Array process improvement.
Work with customer for new package and process development.
Do process optimization on Flip Chip bonder, Underfill Dispensing and Molding process.
Sr. TECHNOLOGY DEVELOPMENT ENGINEER February 2001 to June 2003OSE-USA － San Jose, CA
Developed and qualified CSP, Flip Chip Ball Grid Array (FCBGA).
Eutectic Flow Underfill Process and Au Stud Bump Process (GSB).
Developed and performed projects and experiments to improved processes to increase yield, improved productivity and reduce production cost.
Team Leader on qualification of lead-free project for QFP packages.
Optimized key processes through Design of Experiment (DOE).
Generated TCM / FMEA on key processes as practical approach of eliminating development iteration.
Interface with manufacturing and Process Engineering for package endorsement and process monitoring (SPC).
Sr. PROCESS ENGINEER / TECHNOLGY DEVELOPMENT ENGINEER September 1997 to February 2001ST Assembly and Services Limited － Yishun, Singapore
Start up team of PBGA package.
Developed and qualified EBGA and FEBGA IC packages.
Formulated TCM / FMEA on each key processes.
Conduct buyoff and optimized key processes through DOE.
Benchmarking on machine and material selection.
Handle Molding and Glob top dispensing process.
Published 4 patents for BGA product and process improvement.
PROCESS ENGINEER January 1994 to September 1997Amkor Anam － Muntinlupa City, Philippines
Member start-up team on BGA production line.
Install End of Line process equipments and established process specs.
Team Leader MPCpS Team on PBGA mold process.
Formulated TCM (OCAP, FMEA and Positrol Log ) on Mold process.
Provide process procedures and trained manufacturing, maintenance group and QA for common understanding and accuracy.
Optimized key processes through DOE using SAS Jmp software.
PROCESS ENGINEER May 1991 to December 1993National Semiconductor － Cebu City, Philipinnes
Enhanced / simplified processes to optimized productivity without jeopardizing yield and quality.
Conduct process optimization (DOE ) on Transfer Molding Process.
Generated process specs and procurement specs. for new materials and equipment.
Facilitated EOL yield improvement team.
Member of internal auditor at EOL for ISO 9002 requirements.
Bachelor : SCHOOL/ADDRESS YEAR CURRICULUM, 1991University of Cebu － Cebu City, PhilippinesSCHOOL/ADDRESS YEAR CURRICULUM
Science : Mechanical Engineering
Vocational / Marine
Technology Engineering, 1981Cebu State College of Science and － Cebu City, PhilippinesVocational / Marine
Approved 4 BGA patents at STATS Singapore and pending patents at Vertical Circuits USA. Start up PBGA and FEBGA Amkor Anam Philippines P3 and STATS Singapore. Developed and qualified the Flip Chip Package (FCBGA) at OSE-USA and CORWIL TECHNOLOGY. Molding Compound Cost Reduction Project, certificate of recognition given by National Semiconductor Corporation. Had completed Project Management training at American Management Association at San
Francisco from May 10 to May 12, 2006.
MAJOR ACHIEVEMENTS: Approved 4 BGA patents at STATS Singapore and pending patents at Vertical Circuits USA. Start up PBGA and FEBGA Amkor Anam Philippines P3 and STATS Singapore. Developed and qualified the Flip Chip Package (FCBGA) at OSE-USA and CORWIL TECHNOLOGY. Molding Compound Cost Reduction Project, certificate of recognition given by National Semiconductor Corporation. Had completed Project Management training at American Management Association at San Francisco from May 10 to May 12, 2006. Patents: Patent #: 6403401, 6750534 - Heat Spreader Hole Pin 1 Identifier US Patent Issued: June 12, 2002, STATSChipPAC Patent #: 6432742 - Methods of forming drop-in Heat Spreader US Patent Issued: 2002, STATSChipPAC Patent #: 6284572 - Boat and Assembly Method for Ball Grid Array US Patent Issued: 2002, STATSChipPAC Patent #: 6834658 - BGA Singulated Substrates for MOLD Melamine Cleaning US Patent Issued: 2001, STATSChipPAC. Patent Disclosure on Vertical Interconnect on Stack Dice with Heat Spreader. Patent Disclosure on Vertical Interconnect on Enhance Ball Grid Array. Patent Disclosure on Vertical Interconnect with Underfill on Stack Dice LGA.
CHARACTER REFERENCE :
Available upon request.
3D 4, approach, Auto CAD, Benchmarking, CA, conflict resolution, continuous improvement, Design of Experiment, Engineer, experiments, failure analysis, FTIR, functional, insurance, internal auditor, IQ, ISO, ISO 9002, Team Leader, Mfg, materials, material selection, Mentoring, MES, Excel, Power Point, Microsoft Works, optimization, OQ, packaging, PQ, Process Control, process development, Process Engineering, processes, process equipment, process improvement, procurement, Product Development, prototyping, quality, QA, Real Time, requirement, Safety, SAS, Shadow, six sigma, SPC, statistical process control, Visio