AutoCAD - Cadence Spectre, Spice, ADEXL, VCS, MATLAB, Design Complier, IC Complier, PrimeTime, SpyGlass, QuartusII, Modelsim, Verdi
Computer Skills -MS Word, MS Excel, MS Access, MS PowerPoint, MS Outlook, Photoshop
Programming Languages -System Verilog, Verilog HDL, VHDL, TCL, Perl, C, C++, HTML, SQL, Assembly Language
Language - English, Chinese
Sr. Analog Design Engineer, 11/2011
to Current Intel Corporation – Hudson,
Design DDR 5/4 Tx PHY in 10nm/14nm/22nm FinFet tri-gate process for Intel Xeon/Xeon-Phi server processors. Implement PVT compensation circuits such as slew rate control, impedance control, duty cycle correction circuits and equalization circuits, such as cross-talk cancelation, data dependent jitter cancelation, data dependent swing boost and band-gap/bias generation circuits.
Design DDR 5/4 Clocking PHY in 10nm/14nm/22nm FinFet tri-gate process for Intel Xeon/Xeon-Phi server processors. Implement clock distribution circuits, including DLL, phase interpolator (PI), and clock domain cross (CDC) circuits. Optimize designs to minimize voltage domain crossing jitter, skew, and duty cycle errors.
Lead developing and maintaining DDR 5/4 PHY behavioral models. Write validation testbenches, and executed mixed-signal co-simulations for analog pre-silicon functional verification. Verify electrical compliance to DDR JEDEC SPEC and provided feedback to designers on performance, and design margins. Release behavioral models for higher levels of integration and logic verification. Interact with cross-functional groups to support DDR top level validation.
Develop test plans to validate DDR signal and power integrity. Collaborate with SI/Package team for memory interface modeling, simulation, characterization and design performance optimization. Execute DDR system jitter analysis, including Tx/Rx/CLK jitter analysis and deliver memory interface eyemask to SI team.
Participate in all aspects of DDR 5/4 PHY physical implementation and integration from RTL to GDS. Perform RTL synthesis in Design Complier (DC), DFT stitching, and formal equivalency verification. Perform placement and route through IC complier (ICC), including floor planning, multiple-domain clock and power distribution network design. Perform static timing analysis (STA), layout extraction, noise analysis, power analysis and work with logic design and full-chip integration team to sign off closure for tapeout.
Perform analog circuits mismatch analysis through MonteCarlo simulation and reliability, aging and burnin simulation. Provide analog layout guidance/rules to analog mask designer teams for reducing mismatches/crosstalks, optimizing floorplan/routes, and reducing power supply IR drops.
Debug post-silicon circuit issues, like locating root cause of speeding/critical paths based on results of tATPG to accelerate the post-silicon design fixes.
Provide mentor leadership, direction, coaching, feedback to new team members. Contribute to the selection, interview and hiring process for the team. Drive new team members for the engagement and adherence and help them build self-esteem and confidence and reduce the gap between academic and industry experience.
Staff Associate at Molecular and Microscale Bioengineering Lab, 02/2011
to 05/2011 Columbia University – New York City Development of a new device for diagnosing
sexually transmitted diseases at point-of-care settings in developing
Master of Science: Electrical Engineering,
February 2011 Columbia University, Fu Foundation School of Engineering and Applied Science - New York,
Bachelor of Science: Electronics and Communication Engineering,
June 2009 Sun Yat-sen (Zhongshan) University, School of Information Science and Technology - Guangzhou,
PVT and frequency independent Pico-second edge adjustment design for cross-talk cancellation and duty cycle correction (Pending)