Jessica Claire
Montgomery Street, San Francisco, CA 94105 (555) 432-1000,

VLSI design engineer with 15 years of experience seeking for new opportunities to leverage his skills: robust circuit design, variation analysis, tools and methodologies for interaction between process, library and design flow, low power design, high performance design.

  • Standard Cell Library
  • Robust Circuit Design
  • Circuit Analysis
  • Transistor Parameter Variation
  • Transistor Stress & Aging
  • SOC Design

Additional Information
Design Environment: Spice, Intel proprietary tools, Cadence ADE, Verilog, Design Complier, IC Compiler, PrimeTime.
Design Automation: Perl, TCL, Phyton
Personal attributes: strong analytical and problem solving skills, effective team player, endeavoring new horizons
03/2007 to 03/2016 SOC Design Engineer Intel Corp. | San Jose, CA,

Member of team that delivered line of Intel Core i3/i5/i7 microprocessor families and multiple SOC design families targeted at the full range of mobile devices (from phones to tablets). Contributed on delivery  high performance standard cell libraries for Intel Core products: Westmere 32nm Intel process, Haswell 22nm, Broadwell 14nm, Cannonlake 10nm and low power 14nm libraries for multiple Intel mobile projects. Worked on standard library circuit robustness, analyzing circuits and flows to ensure silicon robustness under the full range of process variability, voltage, temperature and stress. Expertise in transistor variation library collateral, library content definition, process scaling and library impact. Level shifter, clock and custom cells design. Layout and electrical quality verification, library collateral consistency with design flow tools validation, developing and supporting automated tools and flows. Examples of full cycle novel cell processing from cell design to usage in chip design: 1) AOI sequential cell robustness and silicon risk assessment, power benefit estimation, SOC flow experiments resulted in AOI cell insertion by DC and ICC for 14nm low leakage process SOC designs; 2) reduced pin capacitance flop robustness assessment and silicon risk analysis, power benefit estimation resulted in improving of 10nm high performance library. Developed tools examples: 1) unified all cell test case regression system for validation timing library collateral, electrical rule checks and layout quality (DRC, density, cell abutment); 2) automated flow for accounting variation and aging hold time degradation and library collateral generation.

07/2005 to 03/2007 Component Design Engineer Intel Corp. | Austin, TX,

Optimal structure definition, optimal logic style implementation definition, circuit design and driving layout design for Register Files and Translation Lookaside Buffer for high performance 0.45um x86 microprocessor project.

03/2000 to 07/2005 Circuit Design Engineer Intel Corp. | Albuquerque, NM,

Critical block paths analysis and spice simulation. Full custom circuit and layout design of critical microprocessor blocks. Cell-based design – logic design, synthesis, physical design and static timing analysis. Key achievements:

  • Register File full custom circuit and layout design for 300MGz ASIC microprocessor test chip, TSMC 0.18um.
  • Arithmetic Logic Unit logic design and synthesis for 300MGz ASIC microprocessor test chip, TSMC 0.18um.
  • 64 KB L1 cache physical design including floorplan, synthesis, place and route, static timing analysis on 0.18um TSMC library for cell-based 300MGz VLIW microprocessor E3M.
  • Small signal carry propagation 64-bit carry-select adder performance estimation (proof of concept) and full custom circuit design using 0.35um and 0.18um TSMC technology for 1.2GHz full custom processor E2K.
Expected in 2000 Master of Science | Electrical Engineering National Research Nuclear University MEPhI (Moscow Engineering Physics Institute), Moscow, GPA:

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School Attended

  • National Research Nuclear University MEPhI (Moscow Engineering Physics Institute)

Job Titles Held:

  • SOC Design Engineer
  • Component Design Engineer
  • Circuit Design Engineer


  • Master of Science

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