SOC Design Engineer April 2011 to CurrentIntel Corporation － Santa Clara, California
Block level design, floor-planning, synthesis, place & route, static timing analysis for: Ivytown Xeon Server (1.35GHz, 22nm): CSI (500K) Skylake Xeon Server (2.38GHz, 14nm): MC Egress (400K), three DFT blocks (200K) CannonLake Xeon Server (2.52GHz, 10nm): MC Ingress (400K) Responsible for RLS PV convergence including timing, power, quality, noise, RV, FEV and ISS.
Implemented complex logic ECOs for various steppings, including metal-only/FIB edits.
Owned timing, noise and RV convergence for the MC subsystem.
Coded pipeline stages for MC power management logic.
Proposed RTL fixes to enable PV convergence.
Wrote perl scripts for data mining and tcl scripts for automating physical design edits.
Worked closely with RTL Owners, DAs and MDs across time zones.
Mentored an Intern and Recent College Graduate.
Physical Design Engineer November 2008 to April 2011Intel Corporation － Hillsboro, Oregon
Section layout owner and RLS Block Owner for XTM (External Tracking and Memory Arbitration) section (Westmere and Haswell Client).
Developed an efficient floorplan and routing topology in XTM comprising of 16 RLS and Datapath blocks, based on block connectivity and dimensions.
Created ~3500 section edge pins for interface nets crossing 5 neighboring sections.
Defined and solidified port placements for ~8000 internal signals across 16 blocks by negotiating with the block DEs.
Used an FC Interconnect tool to identify and fix routes failing slope and delay checks.
Delivered a high quality section layout for tape in, ahead of time.
As part of the FC Integration team, worked on FC Repeater Break, DFM and ISS.
Performed DC (timing), ICC (Place and Route tool), FEV convergence, power analysis, quality checks and final manual layout cleanup on an RLS block in XTM.
Graduate Technical Intern June 2007 to December 2007Intel Corporation － Chandler, Arizona
Performed transistor aging simulations on 12 Bonnell blocks using Agingsim tool for the analysis of transistor degradation and impact on block performance.
Conducted standard cell library checks, analyzed validation reports, performed characterization for standard cells, ran simulations in Presto for timing/power measurements.
Tools/Applications: Design Compiler, IC Compiler (Place&Route), Galaxy, Parade, Genesys, Safran Operating Systems: Windows, UNIX Languages: PERL, TCL Designed a complete 4Kb one-port SRAM memory bank (schematic and layout) using MOSIS 0.25um process technology.
A standard regenerative sense amplifier was used.
Designed the out-of-order microprocessor issue logic using a CAM-RAM cell approach and compacting queue update logic in a MOSIS 0.25um process technology.
The logic is used to issue a maximum of 4 instructions every clock cycle based on the output of an arbiter which makes available the instructions independent of any possible RAW hazards and issues the oldest four among them.
Designed a low power Multi-bit Viterbi Decoder using MOSIS 0.25um process technology.
Performed power and timing measurements on the schematic and extracted netlist.
Education
Master of Science : October 2008Arizona State UniversityGPA: GPA: 3.54/4.00GPA: 3.54/4.00
Bachelors : May 2006Anna UniversityGPA: GPA: 8.7/10GPA: 8.7/10
