Highly motivated Sales Associate with extensive customer service and sales experience. Outgoing sales professional with track record of driving increased sales, improving buying experience and elevating company profile with target market.
Skills
Guest services
Inventory control procedures
Merchandising expertise
Loss prevention
Cash register operations
Product promotions
Accomplishments
Professional Experience
Senior Staff Design Engineer, 08/2008 - Current Silicon Laboratories Inc. – , ,
8
Significantly contributed in successfully taping out 3 families of Set-Top Box chips primarily focusing on developing the hardware-firmware architecture for security sub-system in the SoC and in establishing compliances to many different industry wide security standards defined by various conditional access vendors like CRI, CCAD, NDS, NAGRA, IRDETO, CONAX and VERIMATRIX.
Lead and owned the delivery of the security sub-system as a hardware digital IP to the SoC team and the security firmware to the Software platform team.
As a verification engineer, the following are the key contributions towards engineering & developmental activities: ◦ Developed UVM based verification architecture and comprehensive verification plans from the architectural requirement specification to cover all the features required to implement a security co-processor for the SoC. ◦ Developed various UVCs including UVM drivers, monitors and scoreboards for various bus interfaces used in the security sub-system. ◦ Developed effective and efficient constrained-random UVM sequences to exercise the design through their corner cases to expose all types of bugs. ◦ Developed functional accurate C model and UVM scoreboards to check the functionality of the design based on the specification. ◦ Performed coverage analysis on the designs including Functional, FSM and Code coverage on the design based on the test patterns generated through UVM sequences. ◦ Developed SystemVerilog based assertions for both black-box and white-box testing of the design. ◦ Created and maintained test regression suites. ◦ Owned C based verification suite for the ROM based firmware along with the development of various C-based cryptographic utilities as required for its verification.
As a design engineer, following are the key contributions towards engineering & developmental activities: ◦ Owned and developed Verilog based RTL design for the ARM based security co-processor. Also developed its functional accurate C model. ◦ Owned and developed Verilog based RTL design for the high-speed symmetric key cryptographic engines and side channel protected cryptographic engines for AES-128/256 and TDES-2, TDES-3 algorithms. ◦ Owned and developed Verilog RTL design for the HW based scalable accelerator module used primarily for handling computationally intensive operations involved during RSA and Elliptic Curve cryptographic operations. Also developed its functional accurate C Model. ◦ Owned the RTL design and the functional accurate C model for the DMA based Memory to Memory cipher operation block capable of handling various symmetric key cryptographic operations in various cipher modes like - ECB, CBC, Counter, Cipher Text Stealing and Local Scrambling modes as defined by various CA vendors. ◦ Owned the RTL design and the functional accurate C model for the Configurable Secure Key Management block providing the secure storage for various symmetric keys by implementing various industry standard secure policies. ◦ Significantly contributed in the architecture of implementing the secured JTAG debug access for the SoC and the secure clock monitoring logic.
As firmware engineer, following are the key contributions towards engineering & developmental activities: ◦ Owned the architecture and development of the ROM based secure boot process for the SoC. ◦ Owned the development of the firmware drivers for the security sub-system. ◦ Owned the development of cryptographic library implementing the following cryptographic algorithms: * RSA based encryption & decryption and signature generation & verification algorithms as required by various DRM standards and security vendors for STB like CCAD, NAGRA and NDS. * Elliptic Curve Cryptography based signature generation/verification algorithms as required by various popular DRM standards like DTCP and PLAYREADY. * MAC based authentication algorithms like OMAC, HMAC and CBC MAC. * Cryptographic protocols implementing secure handling of sensitive keys using a secure digital envelope as required by various DRM solutions. * Secure key ladder operations. ◦ Owned the development and the architecture of the firmware responsible for implementing the cryptographic protocol in compliance with the DTA requirements set aside by the CCAD. ◦ Significantly contributed in defining and practicing the guidelines required for developing a tamper-resistant firmware.
Significantly contributed in getting the STB SoC chips successfully certified for various CA vendors like NDS, NAGRA, CCAD, IRDETO, and VERIMATRIX.
Significantly contributed in successfully taping out two families of Set-Top Box chips and in establishing a high-performance team which enabled us to provide cost-effective technical-competencies in developing various Intellectual Property Cores.
In Leadership role, key contributions includes the following: ◦ Developed and led a high-performing team of 5 engineers with complete ownership of Digital-IPs in the video-subsystem of Set-Top Box IC. ◦ Performing the role of a technical leader by reviewing the work products, allocating resources and assigning tasks & responsibilities to the team and aligning it with team's collective goals & focus. ◦ Technically guided the team on overall architecture for implementation. ◦ Supported Project Manager in project estimation, planning and risk management activities.
As an individual contributor, played a key role for engineering & developmental activities which includes the following: ◦ Development of Architectural Specification, Micro-Architecture and Design for FGS Simulation Module, LVDS Panel-Controller IP and Secure-Video Processing IP with direct consultation with Lead SoC Architect. ◦ Complete Ownership of Video-IPs brought responsibilities ranging from RTL-Design to Synthesis, Static Timing Analysis, Formal verification, Debugging of RTL/gate-level simulation issues and On-Chip Validation of these IPs.
Driven the development of function accurate C/C++ models, Verification environment and developed comprehensive test-plans for verifying these IPs, targeting 100% Functional coverage at Unit-level, and at System-Level.
Presented creative solutions on various critical issues in the chip faced during on-field testing with customers.
Demonstrated quality execution within established timelines and excellent interpersonal skills.
SENIOR DESIGN ENGINEER, 07/2003 - 02/2006 Safran Group – , , ⇒ Significantly contributed in developing and implementing SoC sub-system by analyzing and bringing out best solution for utilizing various IP Modules constituting the sub-system. ⇒ Responsible for Development of PCI Sub-system in an ARM Based SoC chip. ⇒ Developed Low-Level Drivers in ARM for PCI-AHB Bridge and PCI-Controller as a reference to the firmware-team and the customer during post-silicon validation. ⇒ Presented a creative solution for a critical AHB/PCI Bus deadlock condition which rescued the complete project from time to market loss. ⇒ Responsible for development of Color-Management sub-system in FLAT-Panel Display SoC. a. Instrumental in developing new algorithm for Contrast/Brightness control in RTL using Gamut Clipping Algorithm and presenting FPGA board demo to the customers on this new algorithm. b. Developed technical presentations for the customer, board demo presentations and application notes for the SoC Sub-system. Closely coordinating with product managers and providing them with required technical/business specifications for IP Modules constituting SoC sub-systems.
ASIC DESIGN ENGINEER, 01/2001 - 07/2003 Amazon.Com, Inc. – Berkeley, CA, ⇒ Significantly contributed in Research and Development of USB 2.0 IP Core. Represented Wipro Technologies in USB 2.0 Developer's Conference, San Jose, USA and presented working FPGA board presentation for USB 2.0 Device IP Core. ⇒ Responsible for developing digital designs from specification to Verilog/VHDL RTL for USB 2.0 Device and USB 2.0 OTG Core as an individual contributor in the team. ⇒ Developed ASIC Synthesis and STA scripts in TCL for evaluating the various other IP including USB 1.1 OTG, USB 1.1 Host and Wireless LAN IP. ⇒ Practiced CMM-Level 5 quality oriented software engineering guidelines enabling quality release for IP-Core to the customers and the SoC team. ⇒ Authored technical and business oriented specification for all USB based IP products. Assisted marketing team for various customer oriented board demo presentations. ⇒ Provided effective support to marketing team and Project Manager in various customer oriented teleconferences and providing technical consultancy to the customer on USB IP product-line. ⇒ Presented a creative solution to reduce latency in USB IP design and reduce the load on software processing.
Education and Training
Post-Graduate Diploma: VLSI, Expected in 2001 - CENTER FOR DEVELOPMENT OF ADVANCE COMPUTING - , GPA: 2000-2001 CENTER FOR DEVELOPMENT OF ADVANCE COMPUTING, GOVT. OF INDIA. Post-Graduate Diploma in VLSI
Bachelor of Engineering: Electronics and Tele-communication, Expected in 2000 - ARMY Institute of Technology, University of Pune - , GPA: 1996-2000 ARMY Institute of Technology, University of Pune Bachelor of Engineering in Electronics and Tele-communication
Affiliations
Military Experience
01/1996 - 01/2000 ARMY – , 1996-2000 ARMY Institute of Technology, University of Pune Bachelor of Engineering in Electronics and Tele-communication 2000-2001 CENTER FOR DEVELOPMENT OF ADVANCE COMPUTING, GOVT. OF INDIA. Post-Graduate Diploma in VLSI
Certifications
ARM AES
Presentations
Provided effective support to marketing team and Project Manager in various customer oriented teleconferences and providing technical consultancy to the customer on USB IP product-line b. Developed technical presentations for the customer, board demo presentations and application notes for the SoC Sub-system
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