Jessica Claire
Montgomery Street, San Francisco, CA 94105 (555) 432-1000,

Sr Process Development Engineer 10 years of progressive experience leading Product development Process in Device Fabrication (HEMT, LED, Solar Cell), Texturization (Wet and Dry Etching), Furnace Diffusion, Metallization, Passivation (PECVD), Compound Semiconductor Crystal Growth (GaAs, GaN, AlGaN and SiC) by Plasma-MBE, MOCVD, HVPE, RF induced PVT and String Ribbon Reactor. Verifiable strength in leading project to meet customer's expectations, improving process and work procedures in support of Continuous Improvement program. Good interpersonal skill, collaborate with customer teams to identify and remedy quality issues. Core competencies and professional strengths include: Project coordination Creative Problem Resolution (Failure Analysis) Cost Controls/Budget Program Process Development/Implementation/Control Crystal Growth Modeling Software Raw material control (Graphite/Refractory/Liquid Spin coating on Si/Metal purity) Equipment modification Statistics (Six Sigma/Minitab/JUMP)

  • Characterization
  • PL, Double Crystal X-ray Rocking Curve, DLTS, Hall-effect measurement, AFM, RHEED, SEM, I-V, C-V, -PCD, GDMS, ICPMS, FTIR, SIMS, Light Scattering, Laser Scanning, RGA.
  • Deposition System
  • Evaporator, E-Beam Evaporator, Diffusion furnace, CVD, PECVD, MOCVD, MBE, HVPE, PVT, PVD, String Ribbon Reactor.
  • Other tools
  • RIE, Spin Coating, Screen Print.
  • Office Tool
  • SPC, JMP, Minitab, SolidWorks, Six Sigma (Green Belt)

Research and Development

  • Managed voice communications R&D department, resulting in three new products on the market and a generation of an excess of $2M in revenues.

Project Management

  • Supervised project production efforts to ensure projects were completed to company standards, on time and within budget constraints.

Technology Development

  • Designed, built and wired home security system using PLC’s to control and manage sensors, HMI and alarm.

Product Improvement

  • Liaised with [group] to modify and improve overall product performance.
  • Eliminated machine defects through recommendation of machine adjustments.

Professional Experience
11/2008 to 03/2011 Senior Member of Technical Staff At&T | Irvine, CA,
  • Yield improvement (90% to 96%) of String Ribbon Si growth (Gemini2, Quad, 2Win reactor) by ramping 10 % growth rate and cooling profile control Dislocation reduction (from 6E5 to 1E5/cm2) in 80 x 150 mm multicrystalline Si wafer by Boron and Germanium co-doping on Si feedstock to improve Solar Cell Efficiency (0.1%) Set up Qualification Process and Specification of Hot Zone material (graphite and Silicon feedstock) Development of graphite purification to improve Cell Efficiency (gain 0.17%) Thermal modeling to define Hot Zone modification (STR software) Surface Texturing by wet Alkaline and maskless dry RIE to reduce reflectance Phosphorous diffusion process with step annealing to dissolve interstitial impurities in Si (gain 0.2% cell efficiency) Pretreatment of NH3 before SiN:H deposition by PECVD (0.04% efficiency boost) Evaluation of Ag paste Defect mapping method development (PL mapping, X-ray topography, Carrier lifetime, Dislocation) Industry Standard for SIMS, FTIR, GDMS, ICPMS of Silicon and Graphite.
10/2003 to 11/2008 Lead Crystal Growth Process Engineer Amazon | Sherborn, MA,
  • Improved wafer yields by oxidation and thermal design (50 % to 85%) RF induced PVT Reactor Design with flat coil (US patent) Direct SiC growth from powder source by PVT reactor (US and Europe patent) Nondestructive Device Yield prediction method development by Laser Surface Scanning SiC epilayer growth for p-i-n diode by MOCVD CMP, lapping process development Evaluation of AlGaN/GaN on SiC by plasma assisted MBE InGaN/GaN LED device process PECVD passivation Carbonization on Silicon by CVD KOH warm etching for characterization and Cl2-RIE etching for fabrication Develop method to mapping Micropipe using scanning image with Photoshop and Image J (Industry Standard for SiC) Quantitative method of Birefringence defect in SiC using polarizer (co-develop with NREL).
02/2001 to 09/2003 Research Scientist GAN Semiconductor, Inc | City, STATE,
  • GaN growth by Plasma assisted MBE, MOCVD and HVPE Modified MBE, MOCVD, HVPE Reactor Design (All Homemade) InGaN/GaN LED epilayer growth Phto-Electrochemical etching to form porous Si Litho and RIE for selective lateral growth pattern.
08/2000 to 01/2001 Associated Research Scientist LG Electronics | City, , Korea
  • AlGaN/GaN HEMT structure growth by MBE and MOCVD (Target: 1000 cm2/V).
Education and Training
Expected in 2002 Ph.D. of Science | Physics Dongguk University, Seoul, GPA:
Physics Exchange student program with Material Science Department in UC Berkely (1999 ~ 2002) Thesis: A Study on Neutron Transmutation Doped GaN Epilayers Advisor: Tae Won Kang
Expected in 1998 Master of Science | Physics Dongguk University, Seoul, GPA:
Physics A Study on the Photoluminescence of Mg doped p-type GaN grown by Molecular Beam Epitaxy Advisor: Tae Won Kang

National Society of Professional Engineers (NSPE)


Photoshop, C, Cl2, Crystal, FTIR, Image, Laser, Material Science, Exchange, Office, Win, Minitab, modeling, PCD, PL, process development, Scanning, Scientific, SIMS, Six Sigma, SolidWorks, SPC, Specification, type, X-ray

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