Product Development Engineer resume example with 20+ years of experience
JessicaClaire
Montgomery Street, San Francisco, CA94105609 Johnson Ave., 49204, Tulsa, OK Home: (555) 432-1000 - Cell: - resumesample@example.com - -
Experience
03/2015 to 03/2019
Product Development EngineerComcast – College Township, PA,
Path finding definition/execution of qualification on 3DxP memory solutions in FPGA based system.
Performed cross tester data collection to correlation, segment, and resolve discrepancies / issues.
Received award for contributing to reducing mandatory production flow test steps.
Collected data at 800Mhz DDR3 Dual Inline Memory Module and compared to component level Bench and Probe data.
Modified Python scripts ran on FPGA controller and analyzing quality and device reliability data in JMP and Tableau.
03/2012 to 03/2015
Product Development EngineerComcast – Collierville, TN,
Successful Fab qualification transfer of high-volume NOR product line items (3 densities), this enabled a multimillion-dollar savings by utilizing FAB capacity more optimally.
Directed technical meetings, Fail by Owners, screen working group for single bit slow to program.
Received several awards for Electrical and Physical Failure Analysis, Screen definition and implementation, Qualification ownership adhering to JEDEC and ISO guidelines.
03/2006 to 03/2012
Product Development EngineerComcast – Commerce, MI,
Key contributor to defining and executing qualification on world's first Phase Change Memory from first silicon to manufacturing
Owned all of process 804, 90nm products from High Volume Manufacturing perspective
Led Shanghai and Philippines test sites or technical meetings and decisions
Traveled to Philippines test site to lead task force meetings upon L3L3 undershoot issue
Traveled to Shanghai site to give 2 weeks training to collaborating teams
Directed many technical meetings, Fail by Owners, Yield enhancement task force, excursion and screen working groups, and peer code review forums
Key player in resolving most process related issues through electrical and physical failure analysis; an example was taking a wafer effected by a center to edge fail rate and sampling cross sections to show critical dimensions were route cause for required current to be not on target
Root caused and documented feedback to majority of all customer related returns and issues
Received a generous award for proactively qualifying the product to extended temperature -40C to 105C range enabling more customers
Created and delivered training knowledge to Singapore manufacture teams on 6 different engineering disciplines over the course of 2 weeks
03/2000 to 03/2006
Product Quality and Reliability EngineerIntel Corp. – Multiple Cities, WA,
Facilitated qualifications of P804 products through several FAB proliferation quals and contributed significantly to Electrical and Physical Failure Analysis.
Some examples were root cause due to floating node on P804 32M, root causing level shifters were being blown up by excessive Vcc droop P803 32M, wrong powerup sequence killing Vpp power supply on MCP stacks.
Owned several Multi Chip Package qualifications and contributed heavily in test definition, screening and setting test limits using six sigma fundamentals.
Designed many of key screens that led to success corporate goals of cost reduction: test time reduction, yield improvement and screen reduction.
Orchestrated lead in FAB oxide breakdown excursion.
Owned task force level meetings that resulted to saving 475M$ in silicon inventory in F11.
Derived test time savings concept that saved in 14M$ in Advantest purchases worldwide.
Received dozens of awards for accomplishments.
02/1998 to 03/2000
Quality Assurance TechnicianStarbucks – Calumet City, IL,
Conducted internal ISO9000 audits of procedures, policies, SOP, and records.
Performed preventive maintenance and repair on over 150 pieces of test equipment.
Won top award for solving Electro-Static Discharge (ESD) Constant Monitoring System (CMS) that caused waste and havoc throughout company.
I worked with CEO of CMS system and conducted measurements; results were fluorescent light ballast were causing >100v spike on GND line for a specific duration, I modified several monitoring systems, so they didn't give false triggers.
11/1997 to 07/1998
Package Failure Analysis TechnicianIntel Corporation – City, STATE,
Failure analysis on package level 200Mhz networking microprocessor.
Potted and Polished Microprocessors to Photon Hot spot Emission locations and evaluated samples to Scanning Electron Microscope analysis.
Received award for discovering wire bond necking issue.
Executed and troubleshot manufacturing flows on S9K Trillium, C based ATE on microprocessors.
Work History
03/2015 to 03/2019
Product Development Engineer Micron Technology – Folsom, CA
Path finding definition/execution of qualification on 3DxP memory solutions in FPGA based system.
Performed cross tester data collection to correlation, segment, and resolve discrepancies / issues.
Received award for contributing to reducing mandatory production flow test steps.
Collected data at 800Mhz DDR3 Dual Inline Memory Module and compared to component level Bench and Probe data.
Modified Python scripts ran on FPGA controller and analyzing quality and device reliability data in JMP and Tableau.
03/2012 to 03/2015
Product Development Engineer Micron Technology – Folsom, CA
Successful Fab qualification transfer of high-volume NOR product line items (3 densities), this enabled a multimillion-dollar savings by utilizing FAB capacity more optimally.
Directed technical meetings, Fail by Owners, screen working group for single bit slow to program.
Received several awards for Electrical and Physical Failure Analysis, Screen definition and implementation, Qualification ownership adhering to JEDEC and ISO guidelines.
03/2006 to 03/2012
Product Development Engineer Micron Technology – Folsom, CA
Key contributor to defining and executing qualification on world's first Phase Change Memory from first silicon to manufacturing.
Owned all of process 804, 90nm products from High Volume Manufacturing perspective.
Led Shanghai and Philippines test sites or technical meetings and decisions.
Traveled to Philippines test site to lead task force meetings upon L3L3 undershoot issue.
Traveled to Shanghai site to give 2 weeks training to collaborating teams.
Directed many technical meetings, Fail by Owners, Yield enhancement task force, excursion and screen working groups, and peer code review forums.
Key player in resolving most process related issues through electrical and physical failure analysis; an example was taking a wafer effected by a center to edge fail rate and sampling cross sections to show critical dimensions were route cause for required current to be not on target.
Root caused and documented feedback to majority of all customer related returns and issues.
Received a generous award for proactively qualifying the product to extended temperature -40C to 105C range enabling more customers.
Created and delivered training knowledge to Singapore manufacture teams on 6 different engineering disciplines over the course of 2 weeks.
03/2000 to 03/2006
Product Quality and Reliability Engineer Intel Corporation – Folsom, CA
Facilitated qualifications of P804 products through several FAB proliferation quals and contributed significantly to Electrical and Physical Failure Analysis.
Some examples were root cause due to floating node on P804 32M, root causing level shifters were being blown up by excessive Vcc droop P803 32M, wrong powerup sequence killing Vpp power supply on MCP stacks.
Owned several Multi Chip Package qualifications and contributed heavily in test definition, screening and setting test limits using six sigma fundamentals.
Designed many of key screens that led to success corporate goals of cost reduction: test time reduction, yield improvement and screen reduction.
Orchestrated lead in FAB oxide breakdown excursion.
Owned task force level meetings that resulted to saving 475M$ in silicon inventory in F11.
Derived test time savings concept that saved in 14M$ in Advantest purchases worldwide.
Received dozens of awards for accomplishments.
02/1998 to 03/2000
Quality Assurance Technician Level One Communication – Rancho Cordova, Ca
Conducted internal ISO9000 audits of procedures, policies, SOP, and records.
Performed preventive maintenance and repair on over 150 pieces of test equipment.
Won top award for solving Electro-Static Discharge (ESD) Constant Monitoring System (CMS) that caused waste and havoc throughout company.
I worked with CEO of CMS system and conducted measurements; results were fluorescent light ballast were causing >100v spike on GND line for a specific duration, I modified several monitoring systems, so they didn't give false triggers.
11/1997 to 07/1998
Package Failure Analysis Technician Intel Corporation – Folsom, Ca
Failure analysis on package level 200Mhz networking microprocessor.
Potted and Polished Microprocessors to Photon Hot spot Emission locations and evaluated samples to Scanning Electron Microscope analysis.
Received award for discovering wire bond necking issue.
Executed and troubleshot manufacturing flows on S9K Trillium, C based ATE on microprocessors.
Education
Expected in 10/2019
Six Sigma Green Belt Certification: Expert Rating - Online - , GPA:
Expected in 01/2000
Bachelor of Science: Electronic Engineering ITT Technical Institute - Rancho Cordova, CA GPA:
Summary
Semiconductor engineer with over 20 years' experience in multiple engineering disciplines. Worked in Quality and Reliability Assurance, Product Engineering, Product and Package Failure Analysis, Product Validation, and other supporting roles. Proven track record of managing projects large and small as well as successfully collaborating with local and international teams
Highlights
Semiconductor Device Physics
SEM, Microprobe, Scopes, and Bench
Photon Emission Microscopy analysis
MS Office Suite proficient
Manufacturing - from product conception to end of life
Proficient with nearly all lab equipment - scopes, current probes, handheld tools including mechanical, logic analyzers, frequency generators, power supplies
Six Sigma Green Belt
Data collection and Mining using C, Python, PERL, and SQL queries and scripting
LINUX, UNIX
Data engineering using JMP, Tableau
JEDEC, ISO 9000, ISO-TS
ATE - Advantest, Nextest, S9K, IMS, Magnum
Statistics
C, Power supplies
CMS, Power supply
Concept, Python
Controller, Quality
Cost reduction, Scanning
Data collection, Scripting
Dimensions, Scripts
Edge, Six Sigma
Failure Analysis, SOP
IMS, SQL
Inventory, Statistics
ISO, Tableau
ISO 9000, Test equipment
ISO9000, UNIX
LINUX
Logic
Mechanical
Meetings
Memory
Microprocessors
Microprocessor
MCP
MS Office Suite
Networking
PERL
Physics
Policies
Skills
Semiconductor Device Physics
SEM, Microprobe, Scopes, and Bench
Photon Emission Microscopy analysis
MS Office Suite proficient
Manufacturing - from product conception to end of life
Proficient with nearly all lab equipment - scopes, current probes, handheld tools including mechanical, logic analyzers, frequency generators, power supplies
Six Sigma Green Belt
Data collection and Mining using C, Python, PERL, and SQL queries and scripting
LINUX, UNIX
Data engineering using JMP, Tableau
JEDEC, ISO 9000, ISO-TS
ATE - Advantest, Nextest, S9K, IMS, Magnum
Statistics,
C, CMS, concept, controller, cost reduction, data collection, dimensions, edge, Failure Analysis, IMS, inventory, ISO, ISO 9000, ISO9000, LINUX, logic, mechanical, meetings, memory, Microprocessors, microprocessor, MCP, MS Office Suite, networking, PERL, Physics, policies, power supplies, power supply, Python, quality, Scanning, scripting, scripts, Six Sigma, SOP, SQL, Statistics, Tableau, test equipment, UNIX
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