Initiative-taking and collaborative PPA technical lead, experienced in cross-functional assignments spanning across teams, technologies, and hardware-software boundaries. Proven track record as the official voice of product PPA on multiple concurrent projects in fast-paced and high-pressure environments leading up to taping out and shipping cutting-edge products. Demonstrated ability to serve in positions that require leadership presence, strong communication skills, technical intuition, innovation, and midterm time horizon (3+ years) strategic planning. Currently serving as a GPU Product Power and Performance Attainment (PPA) lead at AMD.
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Product Power, Performance, and Area (PPA) attainment lead for mobile GPUs as well as high-end DGPUs. Responsibilities include: working with GPU & SoC architects, software, IP, FW, platform leads, and foundry technology operations to define the winning PPA feature set and configuration || Providing domain targets (e.g., SW Opt., Perf/Clk, STA, LKG, Dynamic power) that support overall program Perf/W targets || Tracking PPA attainment through architectural models, RTL simulation, and IP/SoC emulation || Providing input to and signing off on design tradeoffs || Providing the Perf/W outlook for the shipping product (~2 years out) || Providing Power Management feature ROI analysis and tradeoff.
- (2020-present) Managerial responsibilities of a team of highly-skilled engineers with 20+ years of industry experience (Senior director-level role - served as acting manager during transition): 18-month staffing plan, strategic big-rock technological investment, critical hire recommendation, team charter update, strategic collaboration and methodology initiatives.
- (2019-present) Multiple generations of RDNA family of DGPUs (concept to tape out).
- (2019-Present) Mobile family of GFXIP through AMD-Samsung partnership.
- (2018-2019) Radeon VII gaming, Radeon Instinct MI50/MI60. World's first 7nm gaming, and Machine Intelligence GPUs. Contributed to, coordinated, and engaged with wide-ranging post-silicon PPA activities. The final gaming product exceeded pre-silicon PPA targets to meet the revised targets reflective of the competitive landscape.
- Worked on the pre-silicon mobile GPU kernel driver (scheduling & dispatch, state dump, register protection, memory allocation)
- Developed an automated GPU power and performance profiling framework (sub- 100 microsecond resolution).
- Designed, prototyped, and evaluated two innovative Dynamic Voltage and Frequency Scaling (DVFS) solutions for graphics workloads running on mobile GPUs, improving energy savings and quality of service significantly.
- Led exploration of forward-looking GPU DVFS solutions: software architecture & hardware requirements.
- Power management of mobile GPUs; Reliability modeling and analysis of high performance, multi-core heterogeneous architectures; Fault tolerance and reliability enhancement of emerging nanotechnologies.
- Peer-reviewed publications with ~200 citations. Reviewer for ISCA, IEEE Micro, ICCD, ACM TACO, ITC, ASAP, HPCA, JPDC.
Dissertation: "Dynamic Voltage and Frequency Scaling for 3D Graphics Applications on the State-Of-The-Art Mobile GPUs"
Member of IEEE HKN (Eta Kappa Nu) honor society
Ranked 5th out of 6000 participants in Iran's national exam for M.Sc. studies in Computer Engineering.
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School Attended
- Northeastern University
- Sharif University of Technology
Job Titles Held:
- Principle Member of Technical Staff, Design Eng.
- Senior graphics software engineer
- Graduate Research Assistant
Degrees
- PhD.
- Master of Science
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