I was employed as a HW Design Engineer from 2007 to now specializing in FPGA design for Telecommunication products at Fujitsu Network Communications. During this period of time, I participated in all phases of FPGA development from the conceptual stages to high volume production releases for different product lines. My first project was on an Altera FPGA and I was able to meet all the deadlines of this FPGA. My second project was part of a 10G Ethernet traffic management FPGA. I was responsible for a high speed memory interface controller implemented in a high-end Xilinx FPGA. This was the project which brought me into the high speed world and I saw many problems in the area of signal integrity and timing which I have never seen before. I was fascinated by the high speed world and it inspired me to invent a dynamic high speed QDRII+ memory controller calibration method which was patented in both U.S and Japan. My strong capability was recognized by the company and since then I was appointed as the FPGA lead and so far I have been successfully led two FPGA projects. One was a 10G OTN transponder system with FPGA served as an OTN overhead processor. I successfully led the team to deliver all the features on time even with some of the unexpected staff change in the middle of the project. The other project was a SoC system with a single IC containing both ARM processors and programmable logic served in the control plane of an 800G Date Center Interconnect system. The team I led successfully completed the design and testing within 6 months which became the first FPGA project in the company which was completed in the shortest amount of time.
Project 1: DMU_SOC FPGA Development (FPGA Lead 2015.6 - 2015.12) Quartus II 15.0; NCSim; SignalTap II; Altera Cyclone V 5CSXFC6D6F31I7) This FPGA resides on a Main Control Unit of an 800G System Bandwidth Data Center Interconnect system. The major function of this FPGA includes:
Project 2: ASC-3 FPGA Development (FPGA Lead 2014.6 - 2015.6) Synplify_Pro; ISE 14.6; NCSim; ChipScope; Xilinx Virtex-5 XC5VLX155-FF1136) This FPGA resides on a dual 10G transponder unit (Network: OTU2/2e, Client: OTU2/SONET/10GE) The major function of this FPGA includes:
Project 3: ASC-1 FPGA Development (FPGA Designer 2012.12 - 2014.6) Synplify_Pro; ISE 13.1; NCSim; ChipScope; Xilinx Virtex-5 XC5VLX155-FF1136) This FPGA resides on a muxponder unit (2 Network Ports; OTU2/2e, 16 Client Port: OTU1/SONET/GE)
Project 4: TM48G FPGA Development (FPGA Designer 2010.12 - 2012.12) ISE 12.2; ModelSim SE; ChipScope; Xilinx Virtex-6 XC6VSX315T-FF1156) This FPGA resides on an Ethernet card with two 10GE network ports and 12 1GE client ports with traffic management functions.
Project 5: SFP14_SYNC FPGA Release 5.x, 6.1 and 6.3 (FPGA Designer 2009.1 - 2010.12) Quartus II 7.2; ModelSim SE; Altera Cyclone III EP3C16 484-pin FBGA) This FPGA resides on the same Ethernet card as the TM48G FPGA.
Board related activities: Hardware Design Verification Engineer of Access Products (2007.11 - 2008.12) Performed functional testing for the above FPGAs.
Engineering System and Computing Thesis: A HW/SW codesign approach for Face Recognition by Artificial Neural Networks on FPGAs
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