Jessica Claire
  • Montgomery Street, San Francisco, CA 94105 609 Johnson Ave., 49204, Tulsa, OK
  • H: (555) 432-1000
  • C:
  • Date of Birth:
  • India:
  • :
  • single:
Professional Summary
5+ years of professional experience in Hardware Design & Development. *Experienced with board design, prototyping, PCB layout, component selection, board bring-up, debugging, and functional verification *Experienced in storage I/O infrastructure (HDD, RAID) *RTL design, Mixed signal circuits, simulation, verification, synthesis, place and route *Experienced in verification planning test case development, writing Test benches to simulate the RTL and validated the design *Strong working knowledge VHDL, Verilog, SystemVerilog *Knowledge of Object Oriented Programming concepts, Perl, VBScript, C++ *Excellent with Schematic Capture tools (Orcad Schematic Capture, Allegro, MentorGraphics DxDesigner)
Cadence ORCAD Schematic Capture, PSpice, ModelSim, QuestaSim, MATLAB, Xilinx ISE, Quartus, DxDesigner, Systemvision, ALDEC HDL, Logic Analyzer, Oscilloscope, Labview, Scrutiny, Eye Measurement Tools C++, Visual Basic, VHDL, Verilog, SystemVerilog, Assembly language, Perl, Python, TCL, VBScript Windows, LINUX, UNIX, MAC
Work History
Hardware Design Engineer, 10/2015 - Current
Caci International Inc. Los Angeles, CA,
  • Part of Cisco M-Series Rack servers Hardware design/development team.
  • Designing next generation modular rack servers, responsible for HDD Backplane, RAID, USB, SPI, I2C, SAS/SATA HDD, PCIE Gen3 NVME Drives, working with Intel next generation CPUs on x86 platform.
  • Design new boards /prototypes (HDD Boards), schematic capture, review PCB layout, and manage working with suppliers.
  • Test designs for functionality and power efficiency.
  • Engage mechanical teams, and software team to ensure application compatibility and performance.
  • Design FPGA logic for HDD backplane high speed SAS / PCIE HDD.
  • Work closely with HDD and storage controller vendors to propose, test, develop technology optimized for Cisco storage server designs.
  • Engage deployments team to ensure smooth product introduction.
  • Debug present issues.
  • Plan DVT for designed boards to test and validate functionality includes simulation of logic, Eye Simulation of SAS channels, and stress test.

Design and Analysis Engineer, 10/2012 - 10/2015
Boeing Oak Harbor, WA,
  • I was involved with multiple engineering disciplines in the specification, test, and support of airborne electronic subsystems including ASICs, FPGAs, controls, communications, displays, and processors.
  • Duties

Hardware Design Engineer, 05/2011 - 10/2012
Caci International Inc. Louisville, KY,
  • As part of a small team of medical imaging product professionals, I was responsible for product management, customer relationship, FPGA design, and board level hardware design for new products as well as existing products.
  • I was responsible for design and development PCB design of high speed digital and/or analog boards and systems using Cadence Orcad Schematic Capture consisting of PCI Express, SRAM, DDR2, DDR3 , ADCs, DACs, Power PC, SATA, DVI, HDMI, USB, SCSI, PLL, I2C, Power Modules, LAN, FPGAs, Fiber-Optic transceivers.
  • Designed PCI-Express board and Video processing board for X-ray Image Processing System.
  • Create self checking test bench, use simulation tools like ModelSim to verify design.
  • Developed module in VHDL for their system which involved creating SPI Memory Controller, Power PC high speed communication via SerDes to transfer data from one FPGA to Another, FIFO and DDR memory interface.
  • Synthesis, PAR (Place and Route) for FPGA designs.
  • Establish PCB layout guidelines and oversee the layout and fabrication of the design.
  • Involved in process of Component Management, Symbol & Model library creation, schematic entry guidelines, net listing & BOM (Bill of Material) generation process.
  • Work closely with cross-functional teams for board layout, support, analyze, debug results of characterization to meet goals.

Master of Science: Electrical Engineer (Digital Design), Expected in December 2015
California State University - Northridge,

Bachelor of Science: Electrical Engineer, Expected in May 2011
California State University - Northridge,
Electrical Engineering

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Resume Overview

School Attended

  • California State University
  • California State University

Job Titles Held:

  • Hardware Design Engineer
  • Design and Analysis Engineer
  • Hardware Design Engineer


  • Master of Science
  • Bachelor of Science

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