Montgomery Street, San Francisco, CA94105(555) 432-1000, resumesample@example.com
Professional Summary
Highly motivated Sales Associate with extensive customer service and sales experience. Outgoing sales professional with track record of driving increased sales, improving buying experience and elevating company profile with target market.
Skills
Guest services
Inventory control procedures
Merchandising expertise
Loss prevention
Cash register operations
Product promotions
Work History
2014 to 01/2016DFT EngineerMeta | Dallas, ,
Inserting DFT logic to IP and Verify its functionality.
Formulation of Different DFT techniques required for IP.
Verification of all DFT methodologies inserted in the design.
Programming IEEE1500 controller to configure PLL.
Programming IEEE1500 controller to test PLL, MBIST, etc.
Working on Pattern generation and simulation of scan (stuck-at) patterns
Working on Pattern generation and simulation of Transition patterns.
Worked on tools tetramax, dc_shell, ncsim, etc.
Current to CurrentProject EngineerDart Container Of Michigan | , ,
Experience : 2 years 6 months worked onsite at LSI India Research and Development Pvt.
Ltd LSI India R&D Pvt Ltd designs and develops markets high-performance storage and Networking semiconductors including custom and standard product integrated circuits.
Storage products enable secure movement of digital data to and from host machines, such as servers, personal computers and storage systems to the underlying storage devices on the other hand networking products principally target the wireless infrastructure, enterprise and data center markets.
Projects ÂBRAGI_B0Â It is production chip with a smaller die size than BRAGI .It is a 28nm design with a gate count of around 100M and 3260 memory instances.
It is started to reduce the size of the chip by flattening some modules - Owner of virage patterns (pattern generation and simulation) - Owner of measurement test systems (MTS) which is for converting patterns to tester specific format for delivery - Worked on block level test insertion,bist insertion - Worked on pattern generation and simulation of scan (stuck-at) patterns - Worked on pattern generation for scan tdf, pll_tdf and bist patterns and simulation for both top level and block level - Worked on generation of & simulation coreware patterns like usb2otg, tempsensor, BCAD patterns,etc.
Worked on generation & simulation of PLL ,MRF, SerDes, refio patterns - Worked on latest upf flow for IDDQ pattern generation and simulation - Debugging failing patterns with dve /Verdi - Worked on to4ols like testkompress , fastscan , DFTAdvisor, dc_shell, DFTcompiler, vcs ,dve ,Verdi BRAGI Â It is a 28 nm design project with a gate count of around 100M and 3260 memory instances.
This chip was a test chip which was successfully working on tester.
Owner of measurement test systems (MTS) which is for converting patterns to tester specific format for delivery - Owner of virage patterns (pattern generation and simulation) - Worked on generation of coreware patterns like usb2otg, tempsensor, BCAD patterns.
Worked on PLL ,SerDes, refio patterns - Worked on pattern generation for scan and tdf patterns at both top level and block level - Worked on simulation for scan and tdf patterns at both top level and block level - Debugging failing patterns with dve /Verdi - Did fault analysis for increasing fault coverage/test coverage - Generated 1hot patterns for failing patterns for silcon debug - Generated different pll frequency settings for cleaning shmoo plots of analog pll patterns - Worked on latest upf flow for IDDQ pattern generation and simulation - Generated scripts for automating flow with perl/shell scripting - Worked on tools like testkompress , fastscan , vcs , ncv, Verdi , nWave - Debugged issue related to virage pll patterns when the patterns were failing on tester - corrected testdef file for virage patterns - manually generated rom bist patterns with si_debug WolfGang2 Â It is a 40 nm design project with a gate count of 26.6M.
This project was already on tester and there were some issues with virage patterns and needed regeneration with correct pll settings.
worked on virage pattern silicon debug - regenerated failing virage patterns - MTS to deliver patterns to tester Uguisu  It is a 40 nm design project with a gate count of 89M and 854 memory instances.
It was a production chip.
Owner of scan and pll_tdf patterns - Worked on pattern generation for scan tdf and mbist patterns and simulation for both top level and block level - Debugging failing patterns with dve /Verdi - Did fault analysis for increasing fault coverage/test coverage - Worked on pattern generation and simulation of coreware patterns Training in DFT Methodology in WIPRO - Had 4 months training in VLSI and DFT methodology - In DFT we add extra logic to the circuit to make it testable.
It is required to make circuit more controllable and observable.
Worked on tools like tetramax , dc_shell , vcs.
06/2011 to 2014Project EngineerDart Container Of Michigan | Saint Louis, ,
Owner of virage patterns (pattern generation and simulation)
Owner of measurement test systems (MTS) which is for converting patterns to tester specific format for delivery
Worked on block level test insertion,bist insertion
Worked on pattern generation and simulation of scan (stuck-at) patterns
Worked on pattern generation for scan tdf, pll_tdf and bist patterns and simulation for both top level and block level
Worked on generation of & simulation coreware patterns like usb2otg, tempsensor, BCAD patterns,etc .
Worked on generation & simulation of PLL ,MRF, SerDes, refio patterns
Worked on latest upf flow for IDDQ pattern generation and simulation
Debugging failing patterns with dve /Verdi
Worked on tools like testkompress , fastscan , DFTAdvisor, dc_shell, DFTcompiler, vcs ,dve ,Verdi
Interests
Actively participate in Basketball , Badminton, Squash Clan Leader of the College LAN Gaming team
Expected in 2 2007Control - EIC) HSC (Non-Medical) Budha Dal Public School (CBSE) 80. | AISSE Budha Dal Public School, , GPA:
Expected in Awarded SNS Shining Star my outstanding performance in WIPRO Rewarded Feather in my Cap certificate for my outstanding performance in WIPRO | , , GPA: In wipro I cleared UCF lvl 2.1 with 75/100 marks got Early bird Advantage In wipro I topped UCF lvl 1.1 with 88/100 marks. Secured a job in WIPRO technologies - Amongst 2 out of 700 who was selected for VLSI profile Got rank among top 1.5% students in All India Entrance Examination (AIEEE) and got admission in Thapar University, Patiala. Over 7 million students had given the exam. Qualified IITJEE with 6486 rank.
Expected in 2009POSITIONS OF RESPONSIBILITY Thapar Part of the reception, boarding and lodging committee, presentation, poster design, publicity team in | , , GPA: SATURNALIA annual cultural fest & ARANYA annual techfest
INTERNSHIPS Summer Internship on Project to Design & Fabricate a Stabilized Gimbal System for a Camera
EON which is to be fitted on a UAV January
Additional Information
EXTRA CURRICULAR ACTIVITIES Actively participate in Basketball , Badminton, Squash Clan Leader of the College LAN Gaming team DECLARATION I hereby declare that the above mentioned information is true to the best of my knowledge and belief. PLACE: Noida SIGNATURE
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School Attended
thapar university
AISSE Budha Dal Public School
Job Titles Held:
DFT Engineer
Project Engineer
Project Engineer
Degrees
Bachelors of Engineering
Control - EIC) HSC (Non-Medical) Budha Dal Public School (CBSE) 80.
Awarded SNS Shining Star my outstanding performance in WIPRO Rewarded Feather in my Cap certificate for my outstanding performance in WIPRO
POSITIONS OF RESPONSIBILITY Thapar Part of the reception, boarding and lodging committee, presentation, poster design, publicity team in
