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design verification engineer resume example with 20+ years of experience

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Jessica Claire
Montgomery Street, San Francisco, CA 94105 (555) 432-1000, resumesample@example.com
Professional Summary

Experienced Digital Design Emulation/Verification engineer committed to maintaining cutting edge technical skills and up-to-date industry knowledge. 

 

HARDWARE DEVELOPMENT/ VERIFICATION CortexM3/M4 embedded SOC SDRAM, DRAM, Flash Memory subsystem controllers Wireless infrared communication network controller PC graphics adapter controllers LANGUAGES C, PERL, TCL, BASH shells Self study of OVM user Guide version 2.0.1, System Verilog 3.0 Accellera's Extensions to Verilog, and System Verilog for Verification (second Edition by Chris Spear) OPERATING SYSTEMS Redhat Linux, HP-UX, Sun OS SKILL AREAS Hardware Emulation, Graphic and memory controllers, NC Verilog, Synopsys VCSMX and, Debussy and DVE waveform viewer. SYNOPSYS, Synplify Pro, XILINX, ISE FPGA place and route VI, XEMACS editors, Clear Case, SVN source control tools, CVS, RCS, LSF workload manager, PERL, TK/TCL and GNU C, GNU ddd & gdb Debuggers BASH scripting for automation, Post Silicon validation and characterization procedures.

Skills
  • Pre-Silicon design synthesis for FPGA emulation and validation
  • Post-Silicon design Validation/Characterization of PLL and ADC modules.
  • Project Planning, Organizing, and scheduling Product development
  • Infrared Wireless communication, Graphics adapter, and Memory subsystem controllers.
  • Verilog, Synopsys, and Cadence tools, Debussy wave viewer, VI and XEMACS editors, CVS, LSF, SVN management tools.
  • PERL/C program development
  • BASH Script development
  • UNIX/LINUX system administration tools
  • Windows applications: Microsoft Word, Excel, PowerPoint, and Visio.
Work History
08/2012 to 02/2013 Design Verification Engineer Facebook | Menlo Park, CA,
  • Responsibilities included development of scripts and documentation of flow procedures for generating code coverage for units in the video presentation controller design.
  • The code coverage for line, toggle, and branch was obtained from the suite of tests run on the units.
  • These results were merged and presented to the unit owners for review.
  • The unit owners would evaluate the results and submit new or revised test to cover areas where coverage was not 100 %.
  • Generated coverage data for 15 unit with each unit requiring some 4000 + test each.
  • Developed multi-unit test bench for running system level simulations.
  • This development included BFM models for data input and checker models for data verification on a unit by unit bases.
  • This development also required debug of unit failures which was reported to the unit owners.
  • Established compatibility with third party software products by developing program for modification and integration.
  • Established compatibility with third party software products by developing program for modification and integration.
02/2013 to 03/2014 Emulation/Verification Engineer Accenture Contractor Jobs | Tacoma, WA,
  • Responsibilities included script development; develop best practices procedures, and user support for Emulation/validation of FPGA implemented SOC models.
  • Provide support to users of the company wide SOC Emulation platforms to resolve user issues resulting from procedure and equipment problems for multiple projects.
  • Provided support to model builder engineers to publish models, verify performance and inform users of model availability on the Emulation platforms.
  • Conducted meeting to review open issues seen on specifics models, and assign engineers to verify and report solution or work a rounds that fix the issue.
10/2005 to 05/2012 Verification Engineer National Oilwell Varco Inc | Burkburnett, TX,
  • Responsibilities included design verification test development, and modification.
  • Perform FPGA builds of pre-tape out designs and validate design features, and post-silicon validation for analyzing and reporting results of characterization/validation test.
  • Characterize PLL oscillator accuracy in a thermal column environment under PVT conditions, and report results.
  • Characterized 10 bits, 16 channels ADC offset error at room temperature.
  • Specified and implemented validation flow scripts to automate design validation test environment.
  • The scripts successfully improved the directed test validation flow, and resulted in an improvement of 75% better coverage of post silicon features.
  • Specified and improved the FPGA flow scripting using PERL and Linux scripting language, and the Synplify Pro and Xlinx tools.
  • This resulted in a 3X improvement of the maximum clock speed.
  • Previous maximum clock speed was 6MHz, and the scripting improved the maximum clock speed to 20MHz.
  • These scripts also allowed simulation of the design in the Linux environment, which was a major accomplishment.
2004 to 2005 Design Engineer Silicon Laboratories Inc. | Beaverton, OR,
  • Proposed design changes to improve the performance and operational capabilities of existing instrumentation and equipment.
  • Specified require design modification of an existing FPGA design to improve the FPGA device utilization so that additional design improvements could be implemented.
  • I successfully improved the FPGA device utilization from 95% to 75%.
  • This allowed the design improvement necessary for successful operation of the computer subsystem to be implemented and validated.
2000 to 2003 Senior Staff Design Engineer Silicon Laboratories Inc. | Austin, TX,
  • Provide specifications, RTL design and Directed test cases for verification of a CD-Rom Controller ASIC.
  • Designed and implemented modifications to the CD_ROM Controller to replace asynchronous logic sections of the CD-ROM controller with fully synchronous logic.
  • This allowed DFT (design for test) features to be added.
  • These modifications achieved higher test and functional verification coverage of the design, and produced an independent CD-ROM core module with improved portability and reusability.
  • Assisted in the definition and selection of development tools needed to support ASIC design teams, resulting in a more cost effective and efficient strategy for company wide development teams.
1995 to 2000 Senior Staff Design Engineer Delta Air Lines, Inc. | Providence, RI,
  • Responsibilities included specification, design, and verification of the sub-systems within a CD-ROM Controller ASIC.
  • Developed a strategy for the conversion of the Compass Schematic representation of the CD-ROM controller design into Verilog RTL representation.
  • This resulted in faster turnaround for performance improvements and product releases to production.
  • Modified Compass functional test verification code into Verilog code, resulting in a 100% improvement in functional test generation and maintainability for the CD-ROM decoder.
  • Created design modifications to the memory controller section of the CD-ROM decoder to support 16 bit wide fast-page /EDO mode, DRAM devices, and SDRAM devices.
  • This resulted in higher performance CD-ROM read speeds and cost effective memory solutions for customers.
  • Designed RTL modifications to support CD-ROM speeds in excess of 50X read rate.
1992 to 1995 Senior Engineer Analog Devices, Inc. | Boston, MA,
  • Responsibilities included the design, implementation, and verification of the microprocessor and memory subsystems of the Disk drive Controller ASIC.
  • Specified and developed CPU and Memory/DMA controller interface logic for the next generation of the hard disk controller using Verilog / Synopsys development tools for a custom gate array ASIC.
  • These performance improvements allowed the disk to host transfer rates to improve from 10 to 33 Mega Bytes/sec.
  • The design flow strategy resulted in the controller development cycle being reduced from nine months to three months.
1988 to 1992 R & D Project Leader Honeywell | Georgia, AL,
  • Responsibilities included the development of assemble language programs, the specification and implementation of the logic design for a Wireless infrared LAN adapter.
  • Designed ASIC optical modem chip for the infrared communications products, resulted in IRDA standard.
1986 to 1988 R & D / Production Engineer Helios Systems Incorporated | City, STATE,
  • Responsibilities included the test and debug of third party memory boards for Sun Computer systems.
  • Developed and provided technical support for 12/24 Mega-byte memory board products.
1984 to 1986 Test Development Engineer Hybrid Systems Group | City, STATE,
  • Production test group for hybrid products.
  • Developed Test fixtures and AC/DC parametric test software for the LTX-DX90 test system.
1982 to 1984 Magnetic Test Equipment Operations, Project Leader Memorex Corporation | City, STATE,

Established specification and developed test procedures for the development of a Single Disk Certifier and Servo Writer.The first proto-type was created on schedule and within budget.

1974 to 1982 Project Manager Hewlett-Packard | City, STATE,
  • Designed a versatile extended memory board that enhanced the software development efforts of two company divisions and created two new products.
Current to Current rigid media test equipment manufacturer | , ,

Education
Expected in to to BSEE | Electronics and Computer Sience University of California, Berkeley, CA GPA:
USAF, Honorable discharge, Secret Security Clearance Jessica. Claire Pg. 2
Accomplishments
  • Intel Corporation Inc.
  • Pre-silicon Verification, Test Bench and Code coverage flow development.
  • Texas Instruments Post-silicon Validation and characterization of custom CortexM3 device.
  • Luminary Micro Inc.
  • Pre/Post silicon verification and validation/characterization of SOC with CortexM3 embedded core with I2C, SSI, ETH, USB, and CAN peripherals.
  • Oak Technology Inc. CD-ROM/CD-RW/DVD controller design and verification Quantum Corporation Disk Drive Controller memory interface subsystem design and verification.
  • Photonics Corporation Infrared Wireless Communication Controller design and verification.
  • Helios System Sun WorkStation Memory Module Subsystems design and validation, and test.
  • DBM Corporation PC Graphics display controller design and validation National Semiconductor Device Validation test development on LTX DX90 system.
  • Hewlett-Packard Designed a Keyboard and DRAM memory sub-system for a WorkStation.
Additional Information
  • PATENTS Holder of joint patent for SIMULATING A STORAGE COMPONENT Holder of joint patents for Infrared networking solutions, and applications. AWARDS Five years Service Award - Texas Instruments, Inc. Five years Service Award - Oak Technology, Inc. Recognition of contribution Award - Quantum Corp. Received outstanding Achievements award - National Semiconductor Inc.

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Resume Overview

School Attended

  • University of California

Job Titles Held:

  • Design Verification Engineer
  • Emulation/Verification Engineer
  • Verification Engineer
  • Design Engineer
  • Senior Staff Design Engineer
  • Senior Staff Design Engineer
  • Senior Engineer
  • R & D Project Leader
  • R & D / Production Engineer
  • Test Development Engineer
  • Magnetic Test Equipment Operations, Project Leader
  • Project Manager
  • rigid media test equipment manufacturer

Degrees

  • BSEE

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