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Design Engineer Resume Example

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DESIGN ENGINEER
Professional Profile
Design Engineer with a proven track record of success in [name of industry]. Offer excellence in analytical decision making and product innovation to drive business growth and collaboration. An articulate presenter with the ability to communicate technical information in a clear and concise manner.
Qualifications
  • Verilog, System Verilog
  • Simulation Tools : ModelSim6.3F, NCSim
  • Synthesis Tools : Quartus 9.0
  • Other Languages : C, C++, JAVA
  • Methodology : UVM
  • Desktop Applications : MS Office, Internet Explorer
  • Operating System : Linux, Windows 9x/2000/XP Professional
  • Protocol Knowledge: AMBA AHB, PCI, USB 3.0, xHCI, AHCI, NVMe 1.1b, NVMe 1.2
  • Self-motivated
  • Creative thinking
  • Team player
Experience
Design Engineer
February 2011 to September 2013
Safran Group - Grand Prairie , TX

  • 1. USB3.0 IP Development Client : Internal Team Size : 4 Tool : Modelsim 6.3F, Quartus 9.0, Verilog, AHCI Role : Coding, Synthesis, Verification.
  • Description : Involved in Design of behavioural model of USB 3.0 Device link layer and developed USB device controller link layer behavioural Model.
  • This layer contained the LTSSM (Link Training and Status State Machine), Packet Decoder, Packet framing and CRC calculation.
  • Handling all aspects of link, protocol layers of USB3.0 mass storage Device.
  • 4.
  • xHCI IP Development Client : Cadence U.S Team Size : 4 Tool : Modelsim, Verilog, PCI, xHCI, USB3.0 Role : Coding, Synthesis, Verification.
  • Description : Involved in Design of behavioural model of USB 3.0 Host list processor.
  • This design involves the scheduling of packets to different endpoints in different devices based on round robin algorithm and also handles work items (TRBs) in data structures.
  • Understanding xHCI protocol for setting up test bench and test-cases to test the list processor, transfer ring, command ring and event ring of xHCI host controller .Involved in creating new testcases to exercise xHCI Analysis, debugging and fixing of failed test-cases at IP/Testchip level and filling bugs if any after each release.
Senior Verification Engineer
September 2013 to March 2016
Synopsys, Inc. - Georgia , AL
1.USB3 xHCI Module Level verification - SS Transactor Client : Marvell (U.S) Team Size : 4 Tool : System Verilog, UVM, nWave, Questasim, Perforce Role : Developed Test Environment (API's) Debugged testcases and reported issues Developed Functional Coverage Subscribers Description : USB3 super speed transactor receives work items from scheduler through four list processors (SYNC OUT, SYNC IN, ASYNC OUT, ASYNC IN) and send required USB super speed.For giving work item to transactor, we modelled complete XHCI software behavior, inorder to exercise maximum possible scenarios.
2.USB3 xHCI Module Level verification - TRB Cache Client : Marvell (U.S) Team Size : 4 Tool : System Verilog, UVM, nWave, Questasim, Perforce Methodology : UVM Role : Understanding and various rules of TRB cache DUT.Enhancement of UVM Environment / Testcases for supporting various scenarios (Randomization).Description : USB3 TRB Cache module pre-fetches the transfers TRBs and locally stores them in a cache memory.Handling TRB fetch requests from different schedulers and TRB flush requests from the schedulers and command processors.
3. Synopsys NVMe Host VIP   Client              : Synopsys (U.S) Team Size        : 6 Tool                 : System Verilog, UVM, Perforce Role                 : Developed Test Environment and Sequences.                           Enhancement of UVM Environment / Test-cases for supporting various scenarios                           (Randomization).                                                      Debugged Test-cases and reported issues. Description : The project deals with verifying the Host VIP against the Controller VIP for Spec 1.1b & 1.2 Compliant.  It also involves developing the test layer and finding out bugs in both Host VIP and Controller VIP. 
​
  • 5.
  • Synopsys NVMe Host VIP Client : Synopsys (U.S) Team Size : 6 Tool : System Verilog, UVM, Perforce Role : Developed Test Environment and Sequences.
  • Enhancement of UVM Environment / Test-cases for supporting various scenarios (Randomization).
  • Debugged Test-cases and reported issues.
  • Description : The project deals with verifying the Host VIP against the Controller VIP for Spec 1.1b & 1.2 Compliant.
  • It also involves developing the test layer and finding out bugs in both Host VIP and Controller VIP.
  • 5.
  • Synopsys NVMe Host VIP Client : Synopsys (U.S) Team Size : 6 Tool : System Verilog, UVM, Perforce Role : Developed Test Environment and Sequences.
  • Enhancement of UVM Environment / Test-cases for supporting various scenarios (Randomization).
  • Debugged Test-cases and reported issues.
  • Description : The project deals with verifying the Host VIP against the Controller VIP for Spec 1.1b & 1.2 Compliant.
  • It also involves developing the test layer and finding out bugs in both Host VIP and Controller VIP.
  • 5.
  • Synopsys NVMe Host VIP Client : Synopsys (U.S) Team Size : 6 Tool : System Verilog, UVM, Perforce Role : Developed Test Environment and Sequences.
  • Enhancement of UVM Environment / Test-cases for supporting various scenarios (Randomization).
  • Debugged Test-cases and reported issues.
  • Description : The project deals with verifying the Host VIP against the Controller VIP for Spec 1.1b & 1.2 Compliant.
  • It also involves developing the test layer and finding out bugs in both Host VIP and Controller VIP.
Education
Bachelor of Engineering : Computer Science, 2010Kings Engineering College - Anna University - City, State, IndiaComputer Science
Skills
API, C, C++, Cadence, Hardware, Controller, Client, debugging, fetch, filling, framing, Functional, in Design, Internet Explorer, IP, JAVA, Linux, memory, MS Office, Windows 9, 2000, Operating System, PCI, processors, Coding, scheduling, Simulation, USB, USB 3.0, USB3, USB3.0, Verilog
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Resume Overview

School Attended

  • Kings Engineering College - Anna University

Job Titles Held:

  • Design Engineer
  • Senior Verification Engineer

Degrees

  • Bachelor of Engineering : Computer Science , 2010

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