Design Engineer Resume Example

1.USB3 xHCI Module Level verification - SS Transactor Client : Marvell (U.S) Team Size : 4 Tool : System Verilog, UVM, nWave, Questasim, Perforce Role : Developed Test Environment (API's) Debugged testcases and reported issues Developed Functional Coverage Subscribers Description : USB3 super speed transactor receives work items from scheduler through four list processors (SYNC OUT, SYNC IN, ASYNC OUT, ASYNC IN) and send required USB super speed.For giving work item to transactor, we modelled complete XHCI software behavior, inorder to exercise maximum possible scenarios.

 

2.USB3 xHCI Module Level verification - TRB Cache Client : Marvell (U.S) Team Size : 4 Tool : System Verilog, UVM, nWave, Questasim, Perforce Methodology : UVM Role : Understanding and various rules of TRB cache DUT.Enhancement of UVM Environment / Testcases for supporting various scenarios (Randomization).Description : USB3 TRB Cache module pre-fetches the transfers TRBs and locally stores them in a cache memory.Handling TRB fetch requests from different schedulers and TRB flush requests from the schedulers and command processors.

3. Synopsys NVMe Host VIP   Client              : Synopsys (U.S) Team Size        : 6 Tool                 : System Verilog, UVM, Perforce Role                 : Developed Test Environment and Sequences.                           Enhancement of UVM Environment / Test-cases for supporting various scenarios                           (Randomization).                                                      Debugged Test-cases and reported issues. Description : The project deals with verifying the Host VIP against the Controller VIP for Spec 1.1b & 1.2 Compliant.  It also involves developing the test layer and finding out bugs in both Host VIP and Controller VIP. 

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