Worked with an aggressive team to design several Xeon family processors for High End desktop to Data Center applications utilizing Intel proprietary validation methodologies. Current Experience Includes:
- IP Level Design Validation utilizing industry standard simulation tools paired with UPF for power aware simulation.
- IP Level model build management, with experience in simulation model building, IP level integration, backend tools, and test run tools.
- Testbench design/Architecture using C++, SystemC, UVM and OVM methodologies as well as Intel Derivatives
- Bus Functional Model (BFM) design utilizing multi-language TLM to abstract models into higher level programming languages with greater data modeling capability than SystemVerilog
- Functional coverage development, analysis, and closure.
- Test plan development and management, mentored team to drive test plan closure.
- Maintained IP Level regression lists and contributed to reusable stimulus development
- RTL simulation debug and bug finding.
Resumes, and other information uploaded or provided by the user, are considered User Content governed by our Terms & Conditions. As such, it is not owned by us, and it is the user who retains ownership over such content.
Companies Worked For:
Job Titles Held: