Analog Design Engineer Resume Example

7nm process 2019 - present

• Led the definition, development, implementation, testing debug and characterization phases of the digital wide range PLL to be use across intel products and test chips in the 7nm process node.
• Drove silicon characterization and developed and implemented performance improvements to increase PLL yield to close to 100% in immature silicon.

10nm process 2014 - present

• Technical lead for the Folsom Clocking team, drove a team of 9 engineers to delivered clock IPs for the 10th generation of Intel core processor (launched 2019)
• Defined and implemented a fast lock approach to improve IA core performance and lower power for the 11th generation of Intel core Processor (launched 2020) which led to an improvement on Sysmark score of 1.2%

14nm process 2012 - 2020

• Architect owner and validator for the wide range PLL to be used across all the subsystems in the new 14nm CPU to be launched in 2021.
• Led the team to deliver the analog LCPLLs to be used in the PCI interface as well as the PLLs and DFX circuits in the display unit in the Sky Lake project - 6th generation Intel core processor 14nm (launched in 2015)

22nm process 2009 - 2012

• Designed the analog LCPLL to be used in the PCI interface (gen2 and gen3), took care of the analog blocks, mixed signal simulations and timing closure for the Ivy Bridge project - Intel® Core™ X-series Processors (launched in 2012)
• Led Mixed Signal Validation team to verify PLLs, Regulators, and thermal sensors; wrote required test benches and AMS models to increase validation coverage.
• Drove the test plans definition for silicon testing and the data review for the PLLs in the product.

45nm process 2005 - 2008

• Performed transistor level simulation to define the analog targets for the new metal gate devices to be used in the PLLs.
• Designed the VCOs for Self Biased PLL for the 45nm test chip to be used as a reference for the products.
• Developed a methodology to generated process files based on silicon which helped to root-cause process marginalities impacting PLL lock yield.
• Developed a tool set for PLL and clock silicon characterization for Penryn project - Intel® Core™2 Duo Processor 45nm (launched in 2008).