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Analog Design Engineer Resume Example

Resume Score: 80%

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ANALOG DESIGN ENGINEER
Professional Summary

Motivated and detail-oriented Analog Design Engineer with over 20 years of successful experience in PLL/Clock architecture design and debug. Recognized consistently for performance excellence and contributions to success in SOC's product qualification. Strengths in silicon debug and process marginality backed by several of successful SOCs in the market. Excellent reputation for resolving silicon problems and reducing product DPM in Intel's process lead vehicles.

Skills
  • Excellent Work Ethic
  • Mentoring and Teamwork
  • Strong device Physics knowledge
  • Analog Circuit Design
  • PLL building blocks: VCO/DCO, Band Gap, LDO, Charge pumps
  • Silicon Debug
  • Static timing analysis
  • HDL: Verilog, VHDL
  • CAD: Cadence, Spice, XA, Spectre.
  • Programming: Perl, Python, MATLAB, C++, TCL
Work History
Analog Design Engineer, 05/2005 to Current
Intel Corporation – Folsom, CA

7nm process 2019 - present

  • Led the definition, development, implementation, testing debug and characterization phases of the digital wide range PLL to be use across intel products and test chips in the 7nm process node.
  • Drove silicon characterization and developed and implemented performance improvements to increase PLL yield to close to 100% in immature silicon.

10nm process 2014 - present

  • Technical lead for the Folsom Clocking team, drove a team of 9 engineers to delivered clock IPs for the 10th generation of Intel core processor (launched 2019)
  • Defined and implemented a fast lock approach to improve IA core performance and lower power for the 11th generation of Intel core Processor (launched 2020) which led to an improvement on Sysmark score of 1.2%

14nm process 2012 - 2020

  • Architect owner and validator for the wide range PLL to be used across all the subsystems in the new 14nm CPU to be launched in 2021.
  • Led the team to deliver the analog LCPLLs to be used in the PCI interface as well as the PLLs and DFX circuits in the display unit in the Sky Lake project - 6th generation Intel core processor 14nm (launched in 2015)

22nm process 2009 - 2012

  • Designed the analog LCPLL to be used in the PCI interface (gen2 and gen3), took care of the analog blocks, mixed signal simulations and timing closure for the Ivy Bridge project - Intel® Core™ X-series Processors (launched in 2012)
  • Led Mixed Signal Validation team to verify PLLs, Regulators, and thermal sensors; wrote required test benches and AMS models to increase validation coverage.
  • Drove the test plans definition for silicon testing and the data review for the PLLs in the product.

45nm process 2005 - 2008

  • Performed transistor level simulation to define the analog targets for the new metal gate devices to be used in the PLLs.
  • Designed the VCOs for Self Biased PLL for the 45nm test chip to be used as a reference for the products.
  • Developed a methodology to generated process files based on silicon which helped to root-cause process marginalities impacting PLL lock yield.
  • Developed a tool set for PLL and clock silicon characterization for Penryn project - Intel® Core™2 Duo Processor 45nm (launched in 2008).
Analog Design Engineer, 10/2000 to 05/2005
Intel Corporation – Heredia, Costa Rica, Folsom CA
  • Member of the Latin America Design Services for Desktop Platform Group. Designed PLL charge pumps and performed system parameters tuning to optimize PLL stability for Pentium IV and the last Pentium III CPU.
  • Developed a macro modeling tool for the PLL in C++ with the internal Intel simulator APIs used to characterize and model the new clocking scheme for the 45nm Intel CPU. This tool combined transistors and pseudo-digital electric elements to speed up the simulation.
College Professor, 01/1998 to 12/2007
Universidad Javeriana And Universidad De Los Andes – Bogota, Colombia
  • Lectured classes on VLSI design, tools, flows and methodologies in undergrad and graduate programs and established the IBERCHIP-University relation.

Adjunct Professor Universidad Javeriana - Remote classes, 2004 to 2007

Adjunct Professor Universidad de Los Andes - Bogota, Colombia 1998 to 2000

Assistant Professor Universidad Javeriana - Bogota, Colombia 1998 to 2000

Education
Master of Science: Computer Science And Microelectronics, 04/2000
Universidad De Los Andes - Bogota, Colombia
  • Internship at Laboratory for Analysis and Architecture of Systems (LAAS), Toulouse , France. ECOS-NORD project for a MicroSystems design Methodology
Bachelor of Science: Electronics Engineering, 04/1998
Universidad Javeriana - Bogota, Colombia
  • Awarded best graduate project for "Unidad Movil de comprobacion tecnica"
Patents
  • Circuits and methods for alignment of signals in integrated circuits Method and apparatus to utilize a digital-time-conversion (DTC) based clocking in computing systems
  • Method and apparatus to utilize a digital-time-conversion (DTC) based clocking in computing systems
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Resumes, and other information uploaded or provided by the user, are considered User Content governed by our Terms & Conditions. As such, it is not owned by us, and it is the user who retains ownership over such content.

Resume Overview

Companies Worked For:

  • Intel Corporation
  • Universidad Javeriana And Universidad De Los Andes

School Attended

  • Universidad De Los Andes
  • Universidad Javeriana

Job Titles Held:

  • Analog Design Engineer
  • College Professor

Degrees

  • Master of Science : Computer Science And Microelectronics , 04/2000
    Bachelor of Science : Electronics Engineering , 04/1998

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