Motivated and detail-oriented Analog Design Engineer with over 20 years of successful experience in PLL/Clock architecture design and debug. Recognized consistently for performance excellence and contributions to success in SOC's product qualification. Strengths in silicon debug and process marginality backed by several of successful SOCs in the market. Excellent reputation for resolving silicon problems and reducing product DPM in Intel's process lead vehicles.
7nm process 2019 - present
10nm process 2014 - 2020
14nm process 2012 - 2020
22nm process 2010 - 2012
45nm process 2005 - 2008
Adjunct Professor Universidad Javeriana - Remote classes, 2004 to 2007
Adjunct Professor Universidad de Los Andes - Bogota, Colombia 1998 to 2000
Assistant Professor Universidad Javeriana - Bogota, Colombia 1998 to 2000
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