Goal-oriented, self-motivated Electrical Engineer offering strong synchronous/network embedded system experience from hardware architecture, PCB design, PCB layout, debug, verification, validation, regulatory compliance (NEBS, GR-1089, EMI, Safety, ROHS) and transfer to manufacturing. Strong background in FPGA design/debugging. Demonstrated exceptional problem solving and troubleshooting hardware and software ability. Excellent presentation, documentation and communication (written, oral) skills. A quick learner and has passion to create reliable products.
Strong high speed digital and analog circuit knowledge
familiar with EC, MCO and Deviation process (Agile)
Released company top priority project IGM indoor from hardware architecture, development, implementation, verification to manufacture
Researched and designed IGM (Integrated PTP Grand Master) Outdoor cabling system (inside the dome to lightning protection)
Lead hardware design engineer for several top-selling synchronous systems (TP5000 IMC, TimeCreator IMC)
Innovated new ways to convert Orcad FPGA schematics (Xilinx) to VHDL (Lattice)
Coordinated, resolved and responded to system test PTRs
Senior Hardware Engineer December 2013 to CurrentMicrosemi － San Jose, CA
Defined the hardware architecture (POE, Ethernet GigE PHY, min-OCXO, SmartFusion2 FPGA/SOC, LPDDR, SPI Flash, GPS receiver) of Integrated PTP Grant Master (IGM) Indoor and Outdoor.
Designed, implemented, verified, and debugged IGM Indoor and Outdoor products
Converted SSU2000 Xilinx EOL (End of Life) boards to new Lattice XP2 FPGA based including PCB schematics conversion(level shift, new FPGA pin assignment, new power supply), FPGA conversion from Orcad Schematics to VHDL.
Need understand SSU2000 legacy firmware to trouble-shoot the issues.
Transferred total solution (FPGA, board, etc) to manufacture for continuous top revenue SSU2000 product.
Senior Hardware Engineer October 2001 to November 2013Symmetricom (acquired by Microsemi) － San Jose, CA
Defined the hardware architecture (Cavium CN6010, Ethernet GigE PHY, OCXO, Altera Cyclone4 FPGA, DDR3, eMMC, GPS), selected inter-board connector for cost saving purpose, designed PCB schematics and layout, verified and validated EdgeMaster (PTP boundary clock).
Defined the hardware architecture (MPC8313, FPGA, dual GPS, inter-board communication), designed PCB schematics and layout, designed FPGA VHDL code, verified and validated TP5000E IMC.
Defined the inter-board communication signals and pin assignment between TP5000E IMC, two IOC cards, one IO module and two power modules. Designed, verified, validated and transferred to manufacture.
Defined the hardware architecture (Kontron uP board, CPLD, FPGA, two-way antenna, inter-board communication), designed PCB schematics and layout, designed CPLD and FPGA VHDL code, verified and validated TimeCreator IMC.
Converted TimeHub Clock card from two boards (uP and mother boards) to one single board and EOL Xilinx to Lattice FPGA to save cost. It includes PCB schematics and layout design, verified, validated and transferred to manufacture.
Designed Gowide DSL modem schematics and FPGA (Verilog).
Hardware Engineer January 1997 to October 2001Telmax Communications － Fremont, CA
Hardware Engineer/Team Lead to design SDSL modem for E1, T1 and V.35
Firmware Engineer January 1994 to December 1996Sunrise Telecom － San Jose, CA
Write device driver in C language (screen display, cursor, printing function, etc)
Designed FPGA for the hand-held device
Master : Computer Engineering, 1993University of Southern California － Los Angeles, CA