Successful Product/DFT engineer with over 8 years of professional experience DFT/DFM, New Product Introduction and Semiconductor Engineering Wide knowledge of low power design techniques and familiar with designs with multiple clock domains and gated clocks Good knowledge in the areas of Digital Design, CMOS inverter and logic gates Strong Interpersonal communication and problem solving skills Self motivated and adept at building strong working relationships with coworkers and cross functional teams to achieve project priorities/deadlines
Extensive knowledge in DFT methodology: Mentor's Fastscan and Synopsys TetraMAX
MBIST insertion using DesignWare STAR Memory System
Familiar with Mentor logic vision flow
Verigy 93K and other latest ATE used for silicon bringup
Synopsys/Cadence simulators with waveform debugging tools
Proficiency with Verilog, VHDL, HSPICE, Debussy and Cadence Virtuoso / Schematic Editor
Expert in statistical data analysis of silicon data using jmp and spotfire tools
Knowledge in programming/scripting languages: C, C++, Assembly Languages (MIPS, X86), Perl
Develop DFT methodology and execute the test plans Insert an On-Chip Clocking (OCC) or OPCG controller to use for At-Speed testing with internal clocks.
Modify a scan insertion script to include Scan compression Scan insertion using the Cadence RC or Synopsys DC.
Resolved all DRC violations and added test insertion points to increase the test coverage.
Successfully interpreted the ATPG report file and Increased the test coverage from 99.2% to 99.55% Created a test protocol for a design and customize the initialization sequence Generate test vectors for Stuck-at, Transition delay- TDF, Path delay, IDDQ faults with different clock domains.
Run the gate level vcs/ncverilog simulation with unit delay and SDF timing annotations Analyze and debug the simulation failures.
Work closely with the design team to correct any failures found during simulation Delivered quality and quantity of scan test patterns with high test coverage on time.
Patterns generated at full-chip used for silicon bring-up and production.
Insert BIST using Virage STAR memory system.
Generate/Simulate MBIST patterns Improve yield by including the repair capabilities for the repairable memories in the BIST insertion.
Study the SDC file generated by the SMS tool before using it for the design implemetation.
Incorporated & understand STA timing report.
Mask out non-critical or cross-clock domain paths.
Work with ATE engineer to bring up/ characterize scan patterns Developed and executed an effectively diagnostic flow to identify scan test pattern failures using Yield Assist Testkompress tool.
This flow is helpful to run diagnostic tool for identifying ATPG test failures quickly, enhance and reduce debug time significantly.
Sun Microsystems / Oracle CorporationFebruary 2005 to August 2012Senior Hardware/Product Engineer
Characterizing silicon across PVT, analyzing the tester data and communicating feedback to various cross-functional teams Performed multiple system-to-tester correlations for high-end microprocessor in various test modes.
Shorten the device development cycle time by processing and analyzing the early lot data and took initiative in yield enhancement using the structural tests Significantly reduced the manufacturing cost of processor (almost 5%) by reducing the test time with improve test plan/program Reduced time to market by debugging the scan chain failure problem on silicon by developing the scan segment patterns using JTAG to identify the problematic location Improved performance(by 3%) of the chip by helping designer to Identify the critical timing path on silicon after detailed analysis of silicon circuits using transition test and path delay test, including correlation with silicon data and simulation data including static timing analysis Verified embedded memories using scan based technique called Macrotest for 3 generation of SPARC processor Successfully developed stil program for Inovys tester for multiple products.
Reduced the system debug time by developing the atspeed ATPG ramdump patterns for all memories on the processor Improved 65nm and 40nm product performance greatly by correlating silicon behavior to the process data and identify and process marginality.
Able to optimize the performance of coming product by driving the 28nm product development project with external vendor(TI) Took initiative in yield enhancement for multiple processors by ensuring DFT guidelines/features.
Responsible to develop quality and reliability plan Characterize Serdes test data( Jitter Generation, Transmit Out, Jitter Transfer, Jitter Tolerance and Receiver Sensitivity) using different statistical analysis tools Professional Development One of the few selected candidates depending upon the good performance review for SEED (Sun EngineeringEnrichment & Development) mentoring program.
Through this program I got an opportunity to learn how to adopt a new and different work environment quickly and also a different perspective to tackle technical challenges.
Ontic TechnologiesAugust 2003 to January 2004Verification and Test Engineer Intern
Implemented test plans to verify unit, subsystem, and chip level functionality in a complex SOC environment.
Created constrained random based test-bench and test cases, to ensure adequate feature and code coverage,and to help resolve test failures.
Education and Training
L.D College of EngineeringBachelor of Engineering: Electronics and CommunicationsIndiaElectronics and Communications Digital Integrated Circuits : Analysis and Design of digital integrated circuits; bipolar and MOS inverters and logic gates; semiconductor memories gate arrays; computer aid design; SPICE program DFT concepts for ASIC Designs, Practical application: Covered various DFT techniques such as Scan, ATPG, Boundary Scan and BIST with special emphasis on the ASIC methodology flow. DFT compiler (Scan insertion tool) Advanced Logic Design : Advanced techniques in the design and analysis of sequential circuits, asynchronous circuits, testing techniques, micro-programmed controller, and processor Advanced Computer Architectures : Design of high performance computer architectures Semiconductor Devices : Principles of semiconductor device fabrication, process and simulation, CMOS device physics Designing XILINX CPLDS and FPGAs: Architecture, design techniques and optimization