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Hardware Validation Engineer Resume Example

Resume Score: 65%

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HARDWARE VALIDATION ENGINEER
Profile

Senior hardware engineer with 11 years of pre-silicon verification experience, specializing in memory I/O and socket interconnect on high-end server CPU designs.

Languages & Tools
  • C/C++
  • Perl
  • Specman
  • Verilog
  • SVN/Git/Bitkeeper
  • Linux/shell-scripts
  • Verdi/DVE
  • GDB
  • Object oriented design
Professional Experience

06/2003 to present Intel Hardware Validation Engineer 


2013-present, Xeon (Skylake) series microprocessor 

  • Owner of co-simulation for a new memory protocol over a DDR4 physical interface. Responsible for development of the test plan, Perl based stimulus, C++ test bench components, and BIOS configuration.
  • Developed components to coordinate simulation milestones and configuration between two independent simulators.
  • Coordinating cross-site technical areas related to the memory interface such as BIOS/physical-layer, power management, SMBUS, and RAS.
  • Verification lead of a debug and automation work group establishing guidelines, methodologies, and tool solutions for future products on the road map.

2012-2013, Xeon (Haswell) series microprocessor 

Lead

Professional Experience
Hardware Validation Engineer06/2003 to CurrentIntelHudson, MA

Xeon (Skylake) next generation series microprocessor (2013 - present)

  • Own co-simulation of new memory protocol over DDR4 physical interface. Responsible for development of test plan, Perl based stimulus, C++ test bench components, and configuration.
  • Developed C++ test bench components to coordinate simulation milestones and configuration between two independent RTL simulators.
  • Coordinating multiple technical areas related to the new memory protocol including BIOS/physical-layer, power management features, SMBUS, and RAS.
  • Collaborating with design team in California.

Xeon (Broadwell) next generation series microprocessor(2013 - present)

  • Validating a specific DIMM configuration in co-simulation for a scalable memory interface (SMI). The DIMM BFM does not support the feature, and my testing provides confidence in correct RTL behavior.
  • Collaborating with design team in India.

10nm road map (2013 - present)

  • Leading a debug and automation work group to establish guidelines, methodologies, and tool solutions for all 10nm products.

Xeon (HSX) 22nm next generation series microprocessor (2012-2013)

  • Co-owned co-simulation of multi-socket Quickpath Interconnect.
  • Owned co-simulation of a scalable memory interface (SMI).
  • Lead coordination between DDR-I/O validation team and BIOS team for validation of BIOS in pre-silicon.
  • Created pseudo training flows using Perl stimulus to quickly train the DDR I/O without BIOS for speedier testing of protocol traffic.
  • Enhanced a C++ agent designed as a bridge between BIOS executable and memory BFM to also work in co-simulation.
  • Developed that were the primary vehicle for BIOS testing and found bugs before silicon power-on.


Xeon P1200 series microprocessor (2010-2012)

  • Took initiative and wrote a project agnostic Perl environment for running all future server co-simulations.
  • Co-owned test plan, stimulus, and checking for co-simulation of a scalable memory interface (SMI).
  • Created Specman test content for protocol traffic, BIOS driven physical layer training, power management features, and RAS features.
  • Developed a Specman driver to allow the host simulation to configure a memory buffer during runtime over a set of bus and control signals.
  • Enhanced a Specman agent designed as a bridge between BIOS and the memory BFM to also work in co-simulation with a real RTL memory buffer.
  • Found several RTL and BIOS bugs in co-simulation otherwise not found with a BFM. This greatly shortened post-silicon power-on.


Itanium 9500 series microprocessor (2008-2010)

  • Part of a validation team for both a scalable memory interface (SMI) and Quickpath Path Interconnect.
  • The responsibilities involved initial path clearing, test plan execution, writing focused and exerciser stimulus using BFM agents.
  • In addition, wrote stimulus and drove test plan execution for a co-simulation between the host processor and an I/O hub. Also wrote stimulus and drove test plan execution for a co-simulation between the host processor and a scalable memory interface (SMI).


Itanium 9300 series microprocessor (2005-2007)

  • Part of a validation team for a FBD memory interface. The responsibilities involved initial path clearing, test plan execution, writing focused and exerciser stimulus, checker development, and creating and filling coverage.
  • Owned integration of a FBD BFM with a C++ test bench and developed a memory pre-load feature.
  • Wrote defect/fault detection test patterns used at the manufacturing level.
  • Support person for a set of exerciser maintenance and triage tools/scripts


Validation tools team (2003 - 2005)

  • Supported a C++ simulation run tool used by the entire validation team.
  • Added new flows to the simulation run tool for newly identified cluster model testing.
  • Added features to a simulation event GUI written in C++/Qt and used by validation engineers for simulation debug
Education and Training
Bachelor of Science: Computer Engineering2003PurdueWest Lafayette, IN
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Resume Overview

Companies Worked For:

  • Intel

School Attended

  • Purdue

Job Titles Held:

  • Hardware Validation Engineer

Degrees

  • Bachelor of Science : Computer Engineering 2003

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