with 15 years of experience is looking for new opportunities to leverage skills
according to competencies and beyond.
Robust Circuit Design
Transistor Stress & Aging
VLSI Design Engineer, 04/2007 to 04/2016 Intel Corporation – Hillsboro, OR
Member of x86 core and SoC products team and part of standard library team with key focus on: standard cell circuit robustness, analyzing circuits and flows to ensure silicon robustness under the full range of process variability, temperature, voltage and stress, library scaling for new process, library content definition, standard cell design, standard cell library validation, novel cell experiments with SoC flow.
Developing and support automated tools and flows for library collateral validation, variation collateral generation, datamining and other.
VLSI Design Engineer, 08/2005 to 04/2007 Intel Corporation – Moscow, Russia
Optimal structure definition, optimal logic style implementation definition, circuit design and driving layout design for Register Files and Translation Lookaside Buffer cashes for high performance x86 core processor.
Circuit Designer, 05/2002 to 08/2005 Moscow Center of SPARC Technologies – Moscow, Russia
Optimal structure definition, logic style definition and circuit and layout full custom design of wide range on-chip memories such as Register Files and Small Signal Arrays for low power processor.
ASIC Design Engineer, 11/2000 to 05/2002 Moscow Center of SPARC Technologies – Moscow, Russia
64 KB L1 cache design including synthesis, place and route for ASIC VLIW processor.
Circuit Designer, 04/2000 to 11/2000 Moscow Center of SPARC Technologies – Moscow, Russia
Small swing signal 64 bit ALU full custom circuit design and optimization for high performance VLIW processor.
Master of Science: Electrical Engineering, 2000 National Research Nuclear University MEPhI (Moscow Engineering Physics Institute) - Moscow, Russia Electrical Engineering
Moscow Engineering Physics Institute (MEPhI), Moscow, Russian Federation: