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Sr. Component Design Engineer Resume Example

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SR. COMPONENT DESIGN ENGINEER
Professional Profile
10+ experience in physical design and static timing analysis. Proactive, customer oriented, technically strong and excellent debugging skills.
Qualifications
  • Scripting: Perl, C-Shell, and TCL.
  • CMOS Advance Technology Intel Process nodes: 65nm, 45nm, 32nm, 22nm, 14nm.​

  • Tools: Synopsys Design Compiler (DC/DC-TOPO), Synopsys Primetime (PT), Synopsys ICC Compiler (Placement & Route), Atrenta Spyglass DFT/Spyglass -LP, Cadence (FV), MS-Office, MS-Visio.

Relevant Experience

  • Received Department Impact Award for delivering flawless Integrated System Clock IP design.

  • Received Department Impact Award (Chipset project) for outstanding contribution in meeting frequency convergence on Million Gate Design partition.

  • Received Department Impact Award for 14nm project for providing guidance and driving integration work with Layout team.


Experience
Company NameJune 2013 to CurrentSr. Component Design Engineer
  • Working on 14nm Intel Process technology on modular Phy interface IP going into multiple server & chipset projects with hands on execution and technical lead for the common lane timing, DRC & quality check closure .Involved running synthesis, ICC, floorplanning, Spyglass-LP for UPF quality checks, Primetime for closing lane level timing closure, ERC checks & RV.
  • Lane included both Analog & digital interface so have to work closely with analog team in terms of analog pin placement, FRAM generation, lib file generation, constraint development, Wrote TCL/Perl scripts to do custom timing check on analog -digital interface signals in Primetime Synopsys tool.
  • Intel Corporation, FM - Chipset & Soft IP group Integration Lead for Physical design Nov'12-June'13 Driving execution,methodology & quality excellence for Manageability Engine Soft IP team.
  • Involved in driving issues & timing convergence with different external IP's integrated in ME SIP.
  • Involved as an Interface to SOC customer team for ME SIP timing convergence and worked with RTL team to make any changes needed.
  • Automated the flows for Soft IP synthesis (Synopsys Design Compiler)/Clock domain Crossing/FEV, power estimation using Synopsys primetime power estimation tool by creating standalone runscript using Perl & c-shell for 12 mini IP's that was integrated in ME IP.
  • Introduced a new flow using Atrenta Spyglass DFT tool in the team to get faster scan coverage and help the design team resolves scan related issue ahead of RTL drop to the SOC customer.
  • This helped speed up the work by 2X which was further used by other Soft IP's in the group.
Company NameNovember 2009 to November 2012Technical Lead
  • Hard IP group Lead a team 5 design engineers for High Speed Serial IO hybrid (configurable as USB3/SATA3/PCI-E/GbE).Hands on static timing analysis using Primetime tool, providing mentorship to junior engineers for debugging floorplan&timing related issues, solving congestion and utilization issues.
  • Involved in creating Unified Power Format (UPF) in synopsys design compiler for lower power implementation, worked on power & clock gating requirements with designer and implementing in ICC.
  • Experience in working on extensive hours during the ECO execution mode involving crosstie work with Penang.
  • Knowledgable on doing "what if "analysis in Primetime and fixing timing issues and routing issues in ECO mode.
  • Automated Checkers using TCL/perl scripts for Quality checks on different designs going to Layout integration.
Company NameNovember 2009 to June 2011
  • Lead a team of 3 engineers for creating First generation Hard IP for Integrated System Clock, design spec ~200K gates and ~400 MHz clock frequency based on 32nm.
  • Interacted with customers to understand their design requirements/objectives and develop signoff conditions and milestone checklists appropriate with the design project goals.
  • Worked with project analyst on schedules and requirements for meeting the IP goals on time.
  • Hands on execution ASIC design flow including logic level synthesis, ICC (physical placement and route), Clock tree synthesis (CTS) and Layout verification (LVS/DRC cleanup) using Hercules.
  • Delivered the final GDS to layout for integration.
  • Work closely with RTL, CKT and DFT teams to cover timing aspects of all design features in various PV corners and generation of full chip and block level timing constraints.
  • Performed full static timing verification (Synopsys primetime), signal integrity (noise/glitch analysis) checks, experience with AOCVM (on-chip die variation) and providing the timing in liberty format (libs) to the customer.
  • Client & Component Group.
April 2005 to November 2009Physical Design Engineer
  • Worked on 4 generations of Chipset products as partition owner of ~2.5M gate design involving 32 EBB's and fastest clock being 600Mhz.
  • Owned the complete ASIC design flow execution from RTL2GDS involving synthesis, placement, clock tree synthesis, routing and power optimization.
  • Experience in solving noise timing and glitches in design using Cadence first encounter (routing tool).
  • Have performed ECO's (base & metal) both to solvetiming issues, functional bug fixes and to clean up routing congestion.
  • Efficient in writing TCL scripts to do ECO changes.
Education
University of Wisconsin2004Master of Science (M.S: Electrical Engineering Computer ScienceCityGPA: GPA: 3.85/4.0GPA: 3.85/4.0 Electrical Engineering Computer Science
Cummins College of Engineering2002Bachelor of Engineering (B.E: Electronics & TelecommunicationsCity, IndiaGPA: GPA: 3.5/4.0GPA: 3.5/4.0 Electronics & Telecommunications
Skills
analyst, ASIC, C, Cadence, closing, Client, DC, debugging, DFT, Driving, features, functional, Intel, IP, Layout, logic, MS-Office, optimization, PCI, Perl, Quality, routing, FM, Shell, scripts, Scripting, TCL, USB3, Visio
Additional Information
  • Awards: *Received Department Impact Award for Integrated System clock HIP design in Q3'2011 *Received Department Impact Award (Chipset project) for outstanding contribution in meeting frequency convergence. *Received Department Impact Award for 14nm project for providing guidance and driving integration work with Layout team.
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Resume Overview

School Attended

  • University of Wisconsin
  • Cummins College of Engineering

Job Titles Held:

  • Sr. Component Design Engineer
  • Technical Lead
  • Physical Design Engineer

Degrees

  • Master of Science (M.S : Electrical Engineering Computer Science
    Bachelor of Engineering (B.E : Electronics & Telecommunications

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