Senior DFT Engineer Resume Example Texas Instruments

SENIOR DFT ENGINEER

Summary

Design-for-Test (DFT) specialist and dedicated team player with extensive knowledge of DFT concepts and hands-on expertise with the deployment and implementation of various advanced DFT techniques for low power, high performance and highly integrated SoCs.

Highlights

Strong knowledge in fault modeling Stuck-at, Transition, Path Delay, Gate-Exhaustive, Bridge, IDDQ and other advanced DFT models.
Cadence Encounter Test, Synopsys Tetramax, Mentor Fastscan
Synopsys DFT Compiler and DFTMax, Cadence RTL Compiler
Extensive experience of Gate-level simulation with Synopsys VCS and Cadence NC-Sim simulators

Verilog, VHDL RTL
Proficient in TCL, Perl, C, C++, Linux/Unix shell scripting
Direct experience in silicon bring-up and post-silicon debugging/diagnosis on ATE
Experience in Static timing analysis with PrimeTime
Knowledge in MBist and Boundary Scan

Experience

Texas InstrumentsSeptember 2011 to CurrentSenior DFT Engineer
Stafford, Texas

Drive chip level DFT methodology and implementation for 3+ complex SoCs with multi-million flops from scan insertion, atpg bringup, verification to production pattern generation for stuck-at fault, transition fault, path delay fault and bridge fault.
Responsible for planning compression ratio and atpg partitioning
Drive test coverage enhancement at SoC level and subchip level to achieve low DPPM goal
Ownership of silicon bringup and post-silicon debug and diagnosis. Interface extensively with the product engineering group before and after tapeout to ensure successful silicon bringup and quick turnaround on finding root causes of failures seen on ATE
Developed at-speed test flow for subchip DFT verification with Cadence Encounter Test tool. The flow is adapted by the DFT teams for 4+ SoC design.
Executed at-speed test pattern generation and gate-level simulation for ARM Cortex-A9-based IP
Member of TI Embedded Processor DFT Ramp Review team in charge of reviewing digital SOCs and their adherence to required DFTM methodology, test coverage, test cost, DPPM goal and other quality standards.
Engage with Cadence DFT EDA engineering group to resolve critical tool issues that significantly impact various projects on test quality and product ramp.
Act as technical leader role, provided training on DFT methodology and flow and guided experienced DFT engineers through challenging issues.

Designed and implemented electrical equipment, facilities and systems for commercial and domestic purposes.

Texas InstrumentsSeptember 2007 to August 2011DFT engineer
Stafford, Texas

Key player on the DFT implementation across scan insertion, structural pattern generation, hard macro DFT verification, gate-level simulation.
Drove IP DFT verification and test coverage enhancement. Working closely with RTL designers to improve test coverage and reduce area overhead.
Analyzed and developed more efficient IP DFTM flow methods to increase productivity and reduce DFT implementation time cycles.
Single handedly drove test program deployment by extensively interfacing with product engineering team, physical design team and design verification team, which had directly contribute to excellent quality of design deliverables. On top of that, extended the experience and best practices to other design team.
Gained experience in silicon debug and diagnosis
Mentored and guided new hired DFT engineer and co-op on DFTM methodology, flow and implementation.
Won Growth Super Star award for the outstanding performance in execution

Texas A&M UniversityJanuary 2004 to August 2007Research Assistant, Electronic Design Automation Lab
College Station, Texas

Design and implement a VLSI diagnosis tool that can efficiently diagnose open and short defects in circuits

Designed and implemented a fast and exact critical path algorithm which is more efficient than previous approaches
Proposed a probabilistic ranking method to rank suspects
Applied fault models to further refine the ranking and help localize the defects

Die Product Consortium (DPC) & Texas A&M UniversityNovember 2005 to July 2007Research Assistant, Electronic Design Automation Lab
College Station, Texas

Resolved the fault counting problem - that different ATPG vendors disagree on the fault list and fault coverage metrics

Developed a standard method for fault counting with DPC so that different ATPG tool results can be compared
Co-developed a faulting counting tool in C++
Ran experiments with industry designs and compared ATPG results from Mentor Fastscan and Synopsys Tetramax

Education

Texas A&M University2007Ph.D.: Computer EngineeringCollege Station, TX, US

Dissertation: An Efficient Logic Fault Diagnosis Framework Based on Effect-Cause Approach

Advisor: Duncan M. (Hank) Walker

McNeese State University2002Master of Science: Computer ScienceLake Charles, Texas, USA

Sichuan Univeristy2000Master of Science: Electrical EngineerChengdu, Sichuan, P. R. China

Sichuan University1997Bachelor of Science: Library and Information ScienceChengdu, Sichuan, P. R. China

Resume Overview

Companies Worked For:

Texas Instruments
Texas A&M University
Die Product Consortium (DPC) & Texas A&M University

School Attended

Texas A&M University
McNeese State University
Sichuan Univeristy
Sichuan University

Job Titles Held:

Senior DFT Engineer
DFT engineer
Research Assistant, Electronic Design Automation Lab

Degrees

Ph.D. : Computer Engineering
Master of Science : Computer Science
Master of Science : Electrical Engineer
Bachelor of Science : Library and Information Science

Senior DFT Engineer Resume Example

Resume Score: 60%

Resume Overview

Create a job alert for [job role title] at [location].

Similar Resumes