Product Development Engineer01/2014 to Current Advanced Micro Devices, Inc – Austin, TX
Develop and implement test programs on an ATE (Automatic Test Equipment) platform to validate and debug silicon.
Support silicon validation, characterization, and debug of existing and new VLSI Devices.
Develop and release of manufacturing test programs.
Support product improvement activities, including test time reduction, yield improvement, and conformance to electrical specifications.
Debug and validate Design for Test features.
VLSI and SoC Laboratory at IIT, Chicago July 2013 Task with VLSI circuit analysis, FPGA system implementation and algorithm development under Professor Oruklu's supervision.
Academic Project Experience: Circuit Level Power Reduction: Power Gating Technique Practices and Implementations May 2013 Propose and implement several power gating (PG) techniques to achieve the power optimization of c432 benchmark circuit at circuit level.
Carry Ripple Adder Implementation using Data Driven Dynamic Logic May 2013 Design and implement three different algorithm adder circuits using Data Driven Dynamic Logic (D3L) and Sp- D3L with 45 nm technology node.
Gate Level Power Optimization April 2013 Proposed a methodology to implement an optimizer in gate level of a certain circuit.
Using hierarchical Time slack distribution technique.
Register Transfer Level Power Reduction March 2013 Proposed a methodology to implement the power reduction of a certain circuit.
Using 'Bus Specific Clock', 'Clock Gating', 'Memory Splitting and 'Operand isolation' techniques.
Ultra-Low Power and High Speed Design and Implementation of AES August 2012 and SHA1 Hardware Cores in 65 Nanometer CMOS Technology (DA-Lab) Propose three Register Transfer Level (RTL) circuit techniques and provide RTL soft-Intellectual Property by using the techniques that can be used directly to any ASIC design flow and can be applied for any technology nodes.
Hardware Engineer Intern08/2012 to Current Chicago, IL
Participation of Ultra-Low Power and High Speed Design and Implementation of AES and SHA1 Hardware Cores in 65 Nanometer CMOS Technology.
Harbin Welding and Cutting Products Quality Inspection Institute
Daily testing of the electronic instrumentation, operation of the department's reception work, translation of the documents and external relations with the project partners.
Engineering Intern01/2010 Landi Company Ltd. of First Auto Works
the automatic control system design, programming of the microcontroller software and translation of the daily operation instructions.
Publications: Research on Feature Extraction of Engine Abnormal Sound Signal Based August 2010 on Linear Prediction Analysis, Conference Proceedings of 2010 International Conference on Computer, Mechatronics, Control and Electronic Engineering, pp 76.
Master of Science: Electrical Engineering Computers and Microelectronics5 2013Illinois Institute of Technology-
ILElectrical Engineering Computers and Microelectronics
ECE 429-VLSI Design ECE 583-High Speed Computer Arithmetic ECE 588-CAD Techniques for VLSI Design ECE 742- Digital Systems-on-Chip Design:
Bachelor of Electronic: Information Engineering7 2011Jilin University-
CAD Tool Design for Static Timing Analysis by using Tcl/Tk and C programming April 2012 Analysis circuit slack time; Implement an algorithm by C programming; Design CAD tools for STA engine in VLSI design; Implement Tcl/Tk program to show all the result in command windows.
Image Processing Fundamental Skills March 2012 Process image segmentation, region labeling, region splitting/merging, Fisher discriminant and obtain the region properties with MATLAB.
Design and Synthesis of Carry Propagation Adders January 2012 Development is based on VLSI design concepts including datapath circuit design, standard cell based design flow, and design validation and verification through construction of fast adder architectures in Verilog, to be synthesized using commercial EDA tools from Synopsys and Cadence Design Systems.
Design and Synthesis of Central Processing Units October 2012 Build a 32-bit CPU in Verilog, synthesized using EDA tools from design systems and transform the design implementation from higher abstraction levels.
Construct a nontrivial digital system that can obtain any computation through architectural exploration.
Academic, Photoshop, ASIC, Assembly language, AutoCAD, C, C++, CAD, Hardware, DSP, Digital Signal Processing, Fast, features, Image, Linux, Logic, MATLAB, Memory, Excel, Microsoft Office, PowerPoint, pp, Word, Optimization, PDF, programming, Publications, reception, Research, Scripting, Sound, supervision, system design, Tcl/Tk, Test Equipment, translation, validation, Verilog, VHDL, Video, Visual Studio, VLSI