To obtain challenging software engineering position in the robotics industry, applying creative skills and technical problem-solving to advance the state of the art.
Highlights
Embedded software development
C/C++, Python and MATLAB
Digital hardware and firmware design
FPGA Development
VHDL and Verilog
Integration and Testing
Education
University of PennsylvaniaPhiladelphia, PAExpected in 2013 – –:design - GPA:Four-Bit Synchronous Multiplier Using Modified Baugh-Wooley Algorithm University of Pennsylvania Philadelphia, PA ESE 570 Digital Integrated Circuits and VLSI Fundamentals Final Project 2013 Spring Term Designed and constructed a synchronous 4-bit by 4-bit signed multiplier using Cadence software. Implemented Modified Baugh-Wooley Algorithm. Final design of multiplier chip has a rectangular shape which allows easy integration into a larger design. Final design never failed extensive post-layout simulations and operated at 178.571 MHz which exceeded the project performance requirement of 100 MHz. Wireless Home Automation: Temperature Sensor and Android Application
University of PennsylvaniaPhiladelphia, PAExpected in 2011 – –:Embedded Systems - GPA:University of Pennsylvania Philadelphia, PA CIS 542 Embedded Systems Programming Final Project 2011 Summer Term Developed a system with embedded and mobile components where the mobile component, Android application is able to get data from and send control information to a remote temperature sensor, embedded component. Collaborated with a group of two other students. Back-end and middleware (server and socket programming) were done in C while Android application was done in Java. Acceleration of Cone-Beam X-Ray Computed Tomographic Image Reconstruction Using GPU
University of MichiganAnn Arbor, MIExpected in 2010 – –:design, architecture - GPA:University of Michigan Ann Arbor, MI Independent Study Project 2010 Winter Term C/C++/GPGPU design and implementation of parallelized Feldkemp cone-beam reconstruction algorithm with CUDA. Optimized the implementation of 3-dimensional image reconstruction by utilizing the GPU architecture. Final result was 8.5 fold reduction of processing speed for a 256x248x240-voxel CT image. Robot: Image Processing Robot
University of MichiganAnn Arbor, MIExpected in 2009 – –:Design Project - GPA:University of Michigan Ann Arbor, MI Major Design Project 2009 Winter Term Developed a line detection robot capable of maneuvering to a predetermined destination while robot's vision was captured on a wireless VGA. Collaborated with five other students. Interfaced main FPGA with digital signal processor, CMOS camera, motors and XBees transmitter module (to communicate with wireless VGA). Programmed in C and VHDL to implement DSP and control algorithms and simulated these algorithms in MATLAB. Personally implemented path-finding algorithm in C. Digital DJ
University of MichiganAnn Arbor, MIExpected in 2007 – –:Introduction to Engineering - GPA:University of Michigan Ann Arbor, MI ENGR 100 Introduction to Engineering: Microprocessors & Music Synthesizers Final Project 2007 Winter Term Developed a digital DJ using pedagogical assembly language. Collaborated with a group of three students. Personally implemented a graphics library and GUI windowing system in assembly language.
University of MichiganAnn Arbor, MIExpected in – –B.S.E.:Electrical Engineering - GPA:University of Michigan Ann Arbor, MI B.S.E. Electrical Engineering, Magna Cum Laude, Dean's List Graduated May 2010
University of PennsylvaniaPhiladelphia, PAExpected in – –M.S.:Electrical Engineering - GPA:University of Pennsylvania Philadelphia, PA M.S. Electrical Engineering Graduated December2013
Certifications
ESE
Accomplishments
Lockheed Martin SPOT Award, 2012
University of Michigan Marian Sarah Parker Scholars Program, 2010
University of Michigan University Honors, 2009 Winter Term and 2010 Winter Term
Experience
Bae Systems - Member Engineering Staff, Processor & Digital System Design Center Mclean, VA, 05/2010 - Current
Designed embedded systems software on FPGA-based embedded systems.
Designed, developed, implemented and unit tested back-end digital processor firmware including 10-Gbps Ethernet interface, data processing and integration of SerDes, MDIO and TCP/IP stack firmware.
Developed, configured, integrated and tested (simulation and hardware) major interfaces on the radar antennas on-array digital signal processors.
Experience with interfaces including high-speed serial transceivers, I2C controller, 10-Gbps Ethernet, QDRII+ SRAM, MDIO, SPI, PCI Express, USB, temperature sensor and flash memory. Developed software to configure interfaces and performed hardware testing, integration and verification of these interfaces.
Expanded existing embedded processor system to a dual processor system with additional interfaces including high-speed serial transceivers, control links/interface and 10-Gbps Ethernet interface.
Developed software test code in C/C++, Python, Tcl script and MATLAB to verify interfaces and algorithms on a digital module. Types of components tested included FPGA, CPLD, RFIC, PHY and QDRII+ SRAM.
Supported prototype antenna shelter integration and test effort. Collaborated with a team of approximately thirty engineers. Rapidly absorbed the breadth and complexity of the systems.
Supported schematic design effort through FPGA and CPLD pin assignment and verification.
Designed and developed built-in test capabilities for data interfaces of a FPGA-based system. Designed and implemented algorithm for bit-error rate computation on a FPGA. Integrated pseudorandom number generator algorithm that was implemented using LFSR.
Conducted performance analysis and optimization of FPGA design. Performed FPGA power estimation, integrated temperature sensor firmware and compiled and analyzed FPGA utilization reports.
Streamlined I&T effort by integrating CPLD host logic to enable in-system FPGA programming.
Benchmarked GPU waveform generation on FPGA. Worked on porting and optimizing waveform generation algorithm in C++ and OpenCL using GPU and FPGA.
- Technical Intern , , 05/2008 - 08/2008
May - August 2009
Developed and modified VHDL code for FPGAs and CPLDs and performed hardware simulation and debugging.
Advanced and implemented testing procedures for digital modules.
Participated in development of parts list, design review packages and schematics for digital module design.
Organized trace routing of printed circuit board.
First Merchants Corporation - Computer Operator City, STATE, 05/2007 - 08/2007
Designed, developed and implemented computerized database to store students' information.
Created remote installation image and performed remote operating system installations.
Migrated e-mail accounts to new web mail server.
Affiliations
Lockheed Martin MST Moorestown, NJ Member Engineering Staff, Processor & Digital System Design Center
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University of Michigan
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University of Michigan
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Job Titles Held:
Member Engineering Staff, Processor & Digital System Design Center
