C/C++, VHDL, Embd C, Verilog, Python Designing Tool: Cadence, LVS, DRC, Hspice, LabVIEW, MATLAB, Xilinx ISE, Vivado, ModelSim, ARM Data structures, OS, MS Office
|ASIC, FPGA, VLSI floor-planning, STA, Clock tree synthesis(CTS), Clock Domain Crossing(CDC) Power analysis, Physical & RTL design, Cache design, Advance pipelining, Multicore processors, CPU/micro-architecture, SoC, SRAM, Layout, CMOS, Logic design|
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