Jessica Claire
Montgomery Street, San Francisco, CA 94105 (555) 432-1000,
Professional HW Validation Engineer and high performing technical lead. Proven results connecting overall business needs to engineering and customer specifications. Recognized for expertise in identifying root cause of hardware system issues and transforming them into clear and technical action items. Leader and mentor of high performing technical diverse teams. Key skills include: Processor, Memory, and IO Subsystem Verification Software AIX and Linux virtualization Research and Development Failure Analysis New Product Development Team Leaderships and Development Systems Quality Assurance, Evaluation, and Documentation
  • Hardware: IBM Power Enterprise Systems.
  • OS: AIX, Linux and WINDOWS.
  • Virtualization: KVM, VIOS, Shared Ethernet Adapter (SEA), vSCSI, NPIV, LPAR, VMMs.
  • RAS Design: High Availability design, Quality control, Serviceability Assessments, Human factors, CE field support, PE support, service education delivery, customer service documentation.
  • Protocols: TCP/IP, FTP, SSH, HTTP, I2C, JTAG, and IPMI.
  • Scripting Languages: Python, Perl, shell, and EXPECT.
  • Programming Language: C, C++, Java
  • Test: Hardware Stress, Functional good path, bad path, IO, CPU, Memory, SAN, AIX, Linux, Firmware, virtualization / migration of partition virtualization, creation of test phase, regression, recovery, and ad hoc plan.
  • POWER 8 System, IBM Patent 6,658,599-Method for recovering from a machine check interrupt during runtime, IBM, Austin, TX 6,697,940- Mechanism to disable the gathering of time consuming unnecessary information at boottime, IBM, Austin, TX 6,704,823-Method and apparatus for dynamic allocation of interrupt lines through interrupt sharing, IBM, Austin, TX 2005/0144,533-Method, system, and product for utilizing a power subsystem to diagnose and recover from errors, IBM, Austin, TX.
Professional Experience
01/1998 to 01/2014 Bickford Senior Living | Bloomington, IL,
01/2010 to 01/2014 Development Engineer Entegris, Inc. | , ,
  • Ensured up-time availability of 99.99% and ease of service by architecting design changes within hardware, firmware, and software.
  • Developed and executed functional Hardware Verification to validate RAS system design criteria including processor, memory, and IO subsystem.
  • Led RAS team of 8 technical staff members both onshore and offshore for validation related defects.
  • Work with information development to develop field service documentation and CE education package for in-field diagnosis and repair.
01/2005 to 01/2010 Quality Assurance technical lead | , ,
  • Improved system quality by identifying and addressing system hardware and software defects.
  • Managed multi-year system test team efforts for POWER Server products.
  • Directed international test team of 20 individuals for end-to-end systems test.
  • Realigned schedule deficit of 8 weeks to meet original project date by coordinating team activities, scheduling, tracking, status reporting, and conducting defects meetings.
  • Instrumental in working with hardware design, firmware, and operating systems team to ensure required content released on time.
  • Aligned project schedules, coordinated with other test and development groups, ran internal and external reviews, gathered status, and reported status to upper management.
  • Configured and ordered instrumental Servers and IO drawers needed for full system test coverage.
  • Approved system quality for customer availability to third line management and OEM management.
01/1998 to 01/2004 Systems Verification Engineer | , ,
  • Team lead on IBM pSeries high-end enterprise servers.
  • Led team of 6 engineers that interacted with multiple design, architecture, and test teams to integrate hardware, firmware, and operating systems.
  • Brought system function online through integration of individual hardware and code components.
  • Supported cross-organizational effort of unifying System Integration (HW /FW and OS).
  • Installed and tested focused Operating systems, AIX, Linux distributions: Red Hat Enterprise Linux (RHEL), and SUSE Linux Enterprise Server (SLES).
  • Provided lab and manufacturing support across global sites.
  • Designed experiments by emulating customer environment to recreate field returns.
  • Responsible for debug and improve test quality to prevent future customer failures.
Education and Training
Expected in B.S | Electrical Engineer Rensselaer Polytechnic Institute, Troy, NY GPA:
Electrical Engineer
ad, AIX, C, C++, Hardware, content, CPU, customer service, delivery, diagnosis, documentation, Ethernet, FTP, Functional, hardware design, HTTP, IBM, Java, Languages, Team lead, Linux, meetings, memory, WINDOWS, migration, Enterprise, Operating systems, OS, organizational, Perl, Programming, Protocols, Python, quality, Quality control, RAS, Red Hat, reporting, SAN, scheduling, Servers, shell, Scripting, SSH, system design, System Integration, TCP/IP, validation
Additional Information
  • Outstanding Technical Achievement Award for 750 & 780 POWER 7 System, IBM
  • Outstanding Technical Achievement Award for S824

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