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Design Verification Engineer03/2017 to CurrentMicron, UVM & SOC
Work in verification team as a block owner, responsible for verifying a specific block from test plan to the block verification sign-off.
Silicon bringup and validation.
10/2015 to Current
10/2015 to 03/2017
Work in validation team to bringup and test backend components like encoder, decoder and nand interface, write stress tests in c to test performance and find more rtl bugs.
Debug failures on ASIC boards
Work in verification team to develop test plan and write test in c/c++/system Verilog (UVM) to test a specific block.
Develop functional coverage and code coverage using Questa tools to check the completeness of verification.
Design Verification Engineer / Tidal Systems07/2015 to 10/2015
Clean environment warnings in order to find potential RTL bug (actually found 1 bug).
Add flag in Makefile to turn warnings into fatal errors to keep code clean for the entire project.
Education and Training
Master of Science: eeFEB. 2015columbia UniversityNew York, NY, 美国GPA: 3.85/ 4.0
Bachelor of ScienceJUL. 2013Beihang UniversityBeijingGPA: 3.8/ 4.0