Verification of Data and Control path of a Pipelined LC-3 Microcontroller
Functional Verification was done on the Data and Control path of a Pipelined LC-3 microcontroller with a reduced
instruction set using System Verilog.
The LC3 was tested for bugs in ALU operations, Memory operations and Control operations.
Coverage analysis was done to achieve 100% coverage of the design.
ASIC Design Project: Variable Block Size Motion Estimator
Designed a part of variable block size estimator used in low power H.264 Video Compression Architectures using
The aim of this project was to find motion vectors between two successive motion frames.
Two search frames are provided and we are expected to estimate the motion of the given reference frame in both the
Cache Coherence Protocols
Implemented a trace driven Shared Multiprocessor simulator to implement different Cache Coherence Protocols like
MSI, MESI, MOESI protocols, assuming each processor has a single level private cache.
Different cache configurations were tested with different protocols to find the optimum configuration.
modifications to the existing protocols were done to reduce the Off-Chip bandwidth usage.
Cache and Memory Hierarchy Design
Implemented a flexible Cache and Memory Hierarchy Simulator and used it to study the performance of memory
hierarchies using the SPEC Benchmarks within a fixed area and power budget.
Dynamic Instruction Scheduling
Designed a simulator for an Out of Order superscalar processor based on Tomasulo's Algorithm that fetches,
dispatches and issues N instructions per clock cycle assuming perfect caches and perfect branch predictions.
The simulator was tested for two benchmark traces and different scheduling queue sizes and issue rates.
Per Cycle (IPC) for each case was tested to obtain the configuration with best IPC.
Branch Prediction Simulator
Implemented a Branch Predictor simulator and used it to design branch predictors well suited to the SPECInt 95
3 types of branch predictors were simulated - Hybrid, GShare and Bimodal.
Each of these was tested for three
different traces and the Optimum configuration of the predictors for minimum number of mispredictions was
Experienced Design Verification/Validation Engineer with a demonstrated history of working in the semiconductors
industry. Strong engineering professional skilled in Python, SystemVerilog, Design Verification Testing, Logic Design,
Python, System Verilog, Verilog, C
Verification Methodologies: UVM/OVM
Architecture: ARM64, x86
Operating systems: Windows, UNIX, LINUX, Centos
Tools: Questasim, Modelsim, Verdi, VCS
Debuggers: OCD, BDI, GDB
Design Verification Engineer, 06/2012
to Current Applied Micro Circuit Corporation – Santa Clara
Responsible for silicon bring up, functional and performance validation of Processor Complex (PCP) on
ARM64 server class processors(X-Gene 2 and 3) chips.
Responsible for PVT Characterization of the PCP.
Worked with the RTL team to understand the design and come up with the PCP validation test plan.
Implemented software to run, validate and characterize Memory BIST on PCP macros.
Hands on experience with debuggers like OCD, BDI and development of in house ARM debugger.
Built and ran multiple Linux applications and benchmarks like SpecInt, SpecOMP, LMBench etc on CentOS and in
house version of Linux for performance and functional validation.
Hands on experience with stress and thermal testing.
Worked with systems including various I/Os like Ethernet, PCIe, DDR, USB, SD cards, UART displays and I2C.
Familiar with BIOS, UEFI and Baseboard management controller.
Design Verification Engineer, 06/2011
to 06/2012 Veloce Technologies
Acquired by Applied Micro.
In depth knowledge of CPU and SOC architecture and verification flow.
Responsible for writing and analyzing functional and code coverage for Instruction Cache and Fetch unit and
Floating Point Unit.
Wrote directed and constrained random test cases for ICF and FPU in System Verilog to get functional coverage to
Wrote directed tests in Assembly language to verify the Exception model and Instruction Set Architecture
of ARM64 architecture for server class processor.
Verification Intern, 06/2010
to 08/2010 IBM Corporation – Bangalore,
Masters of Science: Computer Engineering,
May 2011 North Carolina State University - Computer Engineering 3.3/4