Teaching faculty with 15 plus years experience. Areas of expertise include Communication and VLSI .
Theory Subjects and LAB
AT UG LEVEL
1. Optical Communication
2. Digital Communication
3. Communication Theory
4. Linear Integrated Circuits
5. Electronic Circuits-II
6. Principles of Communication
7. Digital Electronics
8. RF and Microwave Engineering
9. Microwave and Optical Lab
10. Communication Systems Lab
11. VLSI Lab
12. Digital Electronics Lab
13. Microprocessor and microcontroller and its Lab
14. Telecommunication Switching
15. Computer Architecture
16. Wireless Communication
17. Circuit theory
18. EDC Lab
AT PG LEVEL
Publications in International and National Conference(5)
1. Ms.K.Krishnaveniand Mrs.C.Kalamani,'An advanced cryptosystem using VLSI simulation',3rd National Conference on (NCSSS – 2008),28th Feb at BIT, Sathy
2. Ms.R.Sherine Jenny and Mrs.C. Kalamani,'Reduction of volume of test data for IP cores using multilevel Huffman coding with parallelism',First national Conference on application of emerging Technology in electrical sciences,9th April, 2009 at Vellalar College of Engineering and Technology, Erode. PP: 506.
3. Mr.V.Mahendrakumar, Mr.P.Lenston Amos, Mrs.C.Kalamani,'Voice controlled zigbee based home automation ‘,National Conference on advances in Computer Vision and Information Technology,12th March, 2012 at GCT, Coimbatore. PP:354.
4. Mr.M.Dharaniand Mrs.C.Kalamani,' Design of decoder using modified hybrid weighted symbol flipping for non-binary LDPC codes', International Conference on Innovations in Information Embedded and Communication Systems-2014, 14th Mar2014 at Karpagam College of Engineering, Coimbatore. Volume: 1, pp. 119-124
5. Ms.K.Nithyaand Mrs.C.Kalamani, 'Test data compression using bit masking and 2n pattern runlength coding', International Conference on Innovations in Information Embedded and Communication Systems-2014, 14th Mar2014 at Karpagam College of Engineering, Coimbatore. Volume: 1, pp. 124-128.
6. Ms.M.Dharaniand Mrs.C.Kalamani,'Modified hybrid weighted symbol flipping decoding for nonbinary LDPC codes', 13thMar 2014 at Kumaraguru College of Technology, Coimbatore.
7. S.Araniand C.Kalamani,'Multistage encoding for test data compression', International conference on Electrical, Instru&Comm Recent Trends and Research Issues (ICE2-RTRI) ,Sri Krishna Institutions, Coimbatore,2-3,January 2015.
8. A.Amutha,G.Dharaniraja, R.Maheswari,Mrs.C.Kalamani,'VHDL based turbo encoder and decoder using cadence',Akshaya College of Engineering and Technology-6.4.2016
9. Devi Sowndarya.K.K,.Kalamani.C,Dr.K.Paramasivam,'Reducing the Test Data Volume by Enhanced Compression code',International Conference on Innovations in Engineering and Technology (ICIET) – 2016,K.L.N college,Madurai.
10. C.Kalamani.V.Abishakkarthick,S,Anitha,K.KavinKumar,'Implementation of low noise and mixer for CMOS Receiver Front ends ‘,International Conference on Interdisciplinary Research innovations in engineering and Technology-march27 and 28 -2018,School of Engg,Ambal Group of Institution,Palladam.
RESEARCH PUBLICATIONS IN INTERNATIONAL JOURNALS
1. Kalamani,C&Paramasivam, K 2013, ‘Survey of Low Power Testing Using Compression Techniques', International Journal of Electronics & Communication Technology, vol. 4, no.4, pp. 13-18.
2. Kalamani,C&Paramasivam, K 2014, ‘A Combined Compatible Block Coding and Run Length Coding Techniques for Test Data Compression',World Applied Sciences Journal, vol. 32, no. 11, pp. 2229-2233. (Annexure-II- 2016.2-20400).
3. Kalamani,C &Paramasivam, K &Dharani, M 2014, ‘A Mixed Selected Selective Huffman Coding and Run length Coding Techniques for Test Data Compression', International Journal of Applied Engineering Research, vol. 9, no. 24, pp. 24003-24010. (Annexure -II- 2014.2- 8565).
4. Kalamani, C&Paramasivam, K 2015, ‘Test Data Compression Using a Hybrid of Bitmask Dictionary and 2n Pattern Runlength Coding Methods',World Academy of Science, Engineering and Technology, vol.9,no.3, pp. 1289-1294. (Annexure -II- 2016.2-20398).
5. Kalamani,C&Paramasivam, K 2017, ‘A Modified Run Length Coding Technique for Test Data Compression Based on Multi-Level Selective Huffman Coding', World Academy of Science, Engineering and Technology, vol. 11, no. 1, pp. 117-120.
6. C.Kalamani.V.Abishakkarthick,S.Anitha,K.KavinKumar, “Design and implementaion of 4 bit multiplier using Fault tolerant Full Adder”, World Academy of Science, Engineering and Technology, Vol.11, No.5, pp.182-192, 2017
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